{"title":"单片差分桥接 T 型线圈","authors":"Giovanni Scarlato;John R. Long","doi":"10.1109/LMWT.2024.3436613","DOIUrl":null,"url":null,"abstract":"Two-pole and three-pole fully differential bridged T-coils applicable to wideband and high-speed integrated circuits are described. T-coil prototypes designed for maximally flat amplitude (MFA) and envelope delay (MFED) responses are characterized. Measured transimpedance bandwidth and group delay of the two-pole MFA design are 43.2 GHz and \n<inline-formula> <tex-math>$7~{\\pm }~2$ </tex-math></inline-formula>\n ps, respectively, across 45 GHz. The three-pole MFED design exhibits 23-GHz bandwidth and \n<inline-formula> <tex-math>$12~{\\pm }~2$ </tex-math></inline-formula>\n-ps group delay across 30 GHz. The bandwidth extension ratio (BWER) compared to each respective unpeaked R-C circuit is \n<inline-formula> <tex-math>$2.43\\times $ </tex-math></inline-formula>\n (MFA) and \n<inline-formula> <tex-math>$2.2\\times $ </tex-math></inline-formula>\n (MFED). Implemented in 22-nm FD-SOI CMOS technology, the T-coil prototypes occupy a chip area of \n<inline-formula> <tex-math>$224 \\times 215~{\\mu {\\text {m}}^{2}}$ </tex-math></inline-formula>\n.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"34 10","pages":"1158-1161"},"PeriodicalIF":0.0000,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Monolithic Differential Bridged T-Coil\",\"authors\":\"Giovanni Scarlato;John R. Long\",\"doi\":\"10.1109/LMWT.2024.3436613\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Two-pole and three-pole fully differential bridged T-coils applicable to wideband and high-speed integrated circuits are described. T-coil prototypes designed for maximally flat amplitude (MFA) and envelope delay (MFED) responses are characterized. Measured transimpedance bandwidth and group delay of the two-pole MFA design are 43.2 GHz and \\n<inline-formula> <tex-math>$7~{\\\\pm }~2$ </tex-math></inline-formula>\\n ps, respectively, across 45 GHz. The three-pole MFED design exhibits 23-GHz bandwidth and \\n<inline-formula> <tex-math>$12~{\\\\pm }~2$ </tex-math></inline-formula>\\n-ps group delay across 30 GHz. The bandwidth extension ratio (BWER) compared to each respective unpeaked R-C circuit is \\n<inline-formula> <tex-math>$2.43\\\\times $ </tex-math></inline-formula>\\n (MFA) and \\n<inline-formula> <tex-math>$2.2\\\\times $ </tex-math></inline-formula>\\n (MFED). Implemented in 22-nm FD-SOI CMOS technology, the T-coil prototypes occupy a chip area of \\n<inline-formula> <tex-math>$224 \\\\times 215~{\\\\mu {\\\\text {m}}^{2}}$ </tex-math></inline-formula>\\n.\",\"PeriodicalId\":73297,\"journal\":{\"name\":\"IEEE microwave and wireless technology letters\",\"volume\":\"34 10\",\"pages\":\"1158-1161\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-08-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE microwave and wireless technology letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10633725/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"0\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE microwave and wireless technology letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10633725/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"0","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Two-pole and three-pole fully differential bridged T-coils applicable to wideband and high-speed integrated circuits are described. T-coil prototypes designed for maximally flat amplitude (MFA) and envelope delay (MFED) responses are characterized. Measured transimpedance bandwidth and group delay of the two-pole MFA design are 43.2 GHz and
$7~{\pm }~2$
ps, respectively, across 45 GHz. The three-pole MFED design exhibits 23-GHz bandwidth and
$12~{\pm }~2$
-ps group delay across 30 GHz. The bandwidth extension ratio (BWER) compared to each respective unpeaked R-C circuit is
$2.43\times $
(MFA) and
$2.2\times $
(MFED). Implemented in 22-nm FD-SOI CMOS technology, the T-coil prototypes occupy a chip area of
$224 \times 215~{\mu {\text {m}}^{2}}$
.