Rapid heat source layout optimization in three-dimensional integrated circuits using artificial neural network reduced-order model in combination with Bayesian optimization

In this study, an efficient optimization framework was developed to determine the parameters of through-silicon vias and the layout of heat sources in three-dimensional integrated circuits (3D ICs), employing an artificial neural network (ANN) reduced-order model in conjunction with a Bayesian optimization (BO) algorithm. The proposed method effectively predicts the temperature distribution in 3D ICs and refines their thermal parameters, offering solutions to thermal management challenges. Latin hypercube sampling was utilized for data sampling, enhancing the previously established rapid thermal analysis method through parameterization of heat source locations. The temperature distribution data for varying hotspot locations in 3D ICs were fitted using an appropriately defined objective function, leading to the development of a reduced-order ANN model that accelerates temperature prediction. The computational results demonstrate that the neural network model exhibits a deviation in predicted values of less than 2%, and the coefficient of determination R² approximately 0.93, underscoring high predictive accuracy. Additionally, the optimization outcomes and the efficiency of the selected BO algorithm were thoroughly evaluated. Notably, the BO algorithm achieved the global optimum in just 4.07 s across 250 iterations, demonstrating an effective power distribution strategy for the 3D ICs model.