建设性平面规划的学习安置顺序

IF 2.2 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Integration-The Vlsi Journal Pub Date : 2024-10-02 DOI:10.1016/j.vlsi.2024.102293
Weiqiang Yao , Yibo Lin , Lin Li
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引用次数: 0

摘要

平面规划是物理设计中一项重要的早期任务。最近,应用基于学习的方法来解决平面规划问题的热潮已经兴起。一种流行的方法是训练一个强化学习(RL)代理在芯片画布上按顺序放置区块。然而,现有的方法主要侧重于学习区块的摆放,依赖启发式规则来确定摆放顺序。与之前的方法不同,我们提出了一种基于 RL 的方法来确定放置顺序。根据图块特征和状态,对代理进行训练,以选择要放置的图块。一旦选择了区块,我们就会枚举序列对捕捉到的所有潜在相对位置,并选择最佳位置。建立布局拓扑后,我们通过线性编程进一步优化线长。实验结果证明了我们所提方法的有效性。在原始线性 MCNC 基准上,与最近一种基于学习的方法相比,我们的方法显著提高了 25.2% 的平均线长。此外,当应用于 MCNC 和 GSRC 的重缩放线性基准时,我们的方法优于最先进的结果,使平均线长减少了 12.5%。
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Learning placement order for constructive floorplanning
Floorplanning is an early and essential task of physical design. Recently, there has been a surge in the application of learning-based methods to tackle floorplanning problem. A prevalent approach involves training a reinforcement learning (RL) agent to sequentially place blocks on a chip canvas. However, existing methods mainly focus on learning block placement, relying on heuristic rules for placement order determination. In contrast to previous approaches, we propose an RL-based method to determine the placement order. Based on block features and states, an agent is trained to select the block for placement. Once a block is selected, we enumerate all potential relative positions captured by sequence pairs and select the optimal placement. After establishing the layout topology, we further optimize wirelength through linear programming. Experimental results demonstrate the effectiveness of our proposed method. On the original-outline MCNC benchmarks, our method achieves a notable 25.2% average improvement in wirelength compared to a recent learning-based method. Additionally, when applied to rescaled-outline benchmarks from MCNC and GSRC, our method outperforms state-of-the-art results, resulting in an average wirelength reduction of 12.5%.
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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