A Computational Digital LDO With Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for Mobile SoC Application

This letter introduces a 10 A computational digital LDO (CDLDO) for mobile SoC application specifically targeting a big CPU core. The proposed CDLDO eliminates the power-FET area overhead by reusing power gating switches (PGSs) already distributed throughout the entire CPU. The CDLDO employs a time-based exponential control (TEC) with a slope detector to achieve fast-transient response and improve stability. Furthermore, a step-back and a negative-step control are introduced to mitigate the effect of the propagation delay between the controller and the PGSs. Additionally, a pre-computational scheme significantly reduces calculation time and relaxes timing constraints during synthesis. The proposed CDLDO is implemented in 3 nm GAAFET CMOS process. An implemented IC of eight distributed CDLDO units provides a maximum load current of 10 A with a current density of 263 A/mm2. The CDLDO shows 94 mV droop under 6.5 A/1 ns load transition.