So-Won Kim, Jae-Hoon Yoo, Won-Ji Park, Chan-Hee Lee, Joung-Ho Lee, Jong-Hwan Kim, Sae-Hoon Uhm, Hee-Chul Lee
{"title":"利用序贯等离子体原子层沉积提高哈夫纳薄膜的电荷捕获性能。","authors":"So-Won Kim, Jae-Hoon Yoo, Won-Ji Park, Chan-Hee Lee, Joung-Ho Lee, Jong-Hwan Kim, Sae-Hoon Uhm, Hee-Chul Lee","doi":"10.3390/nano14201686","DOIUrl":null,"url":null,"abstract":"<p><p>We aimed to fabricate reliable memory devices using HfO<sub>2</sub>, which is gaining attention as a charge-trapping layer material for next-generation NAND flash memory. To this end, a new atomic layer deposition process using sequential remote plasma (RP) and direct plasma (DP) was designed to create charge-trapping memory devices. Subsequently, the operational characteristics of the devices were analyzed based on the thickness ratio of thin films deposited using the sequential RP and DP processes. As the thickness of the initially RP-deposited thin film increased, the memory window and retention also increased, while the interface defect density and leakage current decreased. When the thickness of the RP-deposited thin film was 7 nm, a maximum memory window of 10.1 V was achieved at an operating voltage of ±10 V, and the interface trap density (D<sub>it</sub>) reached a minimum value of 1.0 × 10<sup>12</sup> eV<sup>-1</sup>cm<sup>-2</sup>. Once the RP-deposited thin film reaches a certain thickness, the ion bombardment effect from DP on the substrate is expected to decrease, improving the Si/SiO<sub>2</sub>/HfO<sub>2</sub> interface and thereby enhancing device endurance and reliability. This study confirmed that the proposed sequential RP and DP deposition processes could resolve issues related to unstable interface layers, improve device performance, and enhance process throughput.</p>","PeriodicalId":18966,"journal":{"name":"Nanomaterials","volume":null,"pages":null},"PeriodicalIF":4.4000,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.ncbi.nlm.nih.gov/pmc/articles/PMC11509989/pdf/","citationCount":"0","resultStr":"{\"title\":\"Enhancing Charge Trapping Performance of Hafnia Thin Films Using Sequential Plasma Atomic Layer Deposition.\",\"authors\":\"So-Won Kim, Jae-Hoon Yoo, Won-Ji Park, Chan-Hee Lee, Joung-Ho Lee, Jong-Hwan Kim, Sae-Hoon Uhm, Hee-Chul Lee\",\"doi\":\"10.3390/nano14201686\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p><p>We aimed to fabricate reliable memory devices using HfO<sub>2</sub>, which is gaining attention as a charge-trapping layer material for next-generation NAND flash memory. To this end, a new atomic layer deposition process using sequential remote plasma (RP) and direct plasma (DP) was designed to create charge-trapping memory devices. Subsequently, the operational characteristics of the devices were analyzed based on the thickness ratio of thin films deposited using the sequential RP and DP processes. As the thickness of the initially RP-deposited thin film increased, the memory window and retention also increased, while the interface defect density and leakage current decreased. When the thickness of the RP-deposited thin film was 7 nm, a maximum memory window of 10.1 V was achieved at an operating voltage of ±10 V, and the interface trap density (D<sub>it</sub>) reached a minimum value of 1.0 × 10<sup>12</sup> eV<sup>-1</sup>cm<sup>-2</sup>. Once the RP-deposited thin film reaches a certain thickness, the ion bombardment effect from DP on the substrate is expected to decrease, improving the Si/SiO<sub>2</sub>/HfO<sub>2</sub> interface and thereby enhancing device endurance and reliability. This study confirmed that the proposed sequential RP and DP deposition processes could resolve issues related to unstable interface layers, improve device performance, and enhance process throughput.</p>\",\"PeriodicalId\":18966,\"journal\":{\"name\":\"Nanomaterials\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":4.4000,\"publicationDate\":\"2024-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://www.ncbi.nlm.nih.gov/pmc/articles/PMC11509989/pdf/\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Nanomaterials\",\"FirstCategoryId\":\"88\",\"ListUrlMain\":\"https://doi.org/10.3390/nano14201686\",\"RegionNum\":3,\"RegionCategory\":\"材料科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"CHEMISTRY, MULTIDISCIPLINARY\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Nanomaterials","FirstCategoryId":"88","ListUrlMain":"https://doi.org/10.3390/nano14201686","RegionNum":3,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"CHEMISTRY, MULTIDISCIPLINARY","Score":null,"Total":0}
引用次数: 0
摘要
作为下一代 NAND 闪存的电荷捕获层材料,二氧化铪正受到越来越多的关注。为此,我们设计了一种新的原子层沉积工艺,使用顺序遥控等离子体(RP)和直接等离子体(DP)来制造电荷捕获存储器件。随后,根据使用顺序遥控等离子体和直接等离子体沉积工艺沉积的薄膜厚度比分析了器件的运行特性。随着最初 RP 沉积薄膜厚度的增加,存储器窗口和保持率也随之增加,而界面缺陷密度和漏电流则有所下降。当 RP 沉积薄膜的厚度为 7 nm 时,在 ±10 V 的工作电压下可达到 10.1 V 的最大存储窗口,界面陷阱密度 (Dit) 达到 1.0 × 1012 eV-1cm-2 的最小值。一旦 RP 沉积薄膜达到一定厚度,DP 对基底的离子轰击效应就会减弱,从而改善 Si/SiO2/HfO2 界面,进而提高器件的耐久性和可靠性。这项研究证实,建议的 RP 和 DP 顺序沉积工艺可以解决与不稳定界面层有关的问题,改善器件性能,并提高工艺吞吐量。
Enhancing Charge Trapping Performance of Hafnia Thin Films Using Sequential Plasma Atomic Layer Deposition.
We aimed to fabricate reliable memory devices using HfO2, which is gaining attention as a charge-trapping layer material for next-generation NAND flash memory. To this end, a new atomic layer deposition process using sequential remote plasma (RP) and direct plasma (DP) was designed to create charge-trapping memory devices. Subsequently, the operational characteristics of the devices were analyzed based on the thickness ratio of thin films deposited using the sequential RP and DP processes. As the thickness of the initially RP-deposited thin film increased, the memory window and retention also increased, while the interface defect density and leakage current decreased. When the thickness of the RP-deposited thin film was 7 nm, a maximum memory window of 10.1 V was achieved at an operating voltage of ±10 V, and the interface trap density (Dit) reached a minimum value of 1.0 × 1012 eV-1cm-2. Once the RP-deposited thin film reaches a certain thickness, the ion bombardment effect from DP on the substrate is expected to decrease, improving the Si/SiO2/HfO2 interface and thereby enhancing device endurance and reliability. This study confirmed that the proposed sequential RP and DP deposition processes could resolve issues related to unstable interface layers, improve device performance, and enhance process throughput.
期刊介绍:
Nanomaterials (ISSN 2076-4991) is an international and interdisciplinary scholarly open access journal. It publishes reviews, regular research papers, communications, and short notes that are relevant to any field of study that involves nanomaterials, with respect to their science and application. Thus, theoretical and experimental articles will be accepted, along with articles that deal with the synthesis and use of nanomaterials. Articles that synthesize information from multiple fields, and which place discoveries within a broader context, will be preferred. There is no restriction on the length of the papers. Our aim is to encourage scientists to publish their experimental and theoretical research in as much detail as possible. Full experimental or methodical details, or both, must be provided for research articles. Computed data or files regarding the full details of the experimental procedure, if unable to be published in a normal way, can be deposited as supplementary material. Nanomaterials is dedicated to a high scientific standard. All manuscripts undergo a rigorous reviewing process and decisions are based on the recommendations of independent reviewers.