{"title":"传输线脉冲应力下芯片级硅基 MOSFET 中点状缺陷的演变","authors":"Xinyuan Zheng;Huiying Li;Yibo Ning;Chengbing Pan;Kai Wang;Lixia Zhao","doi":"10.1109/TED.2024.3466840","DOIUrl":null,"url":null,"abstract":"In this study, the electrical performance and evolution of point defects in chip-level Silicon-based MOSFET under transmission line pulse (TLP) stress were investigated. The experimental results show that the threshold voltage decreased by 9.8%, and the output saturation current increased by 5.9% after the stress. An intrinsic point defect with an energy level of \n<inline-formula> <tex-math>$0.25~\\pm ~0.05$ </tex-math></inline-formula>\n eV in Si-based MOSFET chips was observed by using deep-level transient spectroscopy (DLTS), which shifted to \n<inline-formula> <tex-math>$0.37~\\pm ~0.05$ </tex-math></inline-formula>\n eV after the stress. The increase of the trap energy level would reduce the holes at the Si/SiO2 interface, and herein the threshold voltage reduced. This work helps to further understand the evolution of point defects in Si-based MOSFET chips.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6958-6962"},"PeriodicalIF":2.9000,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Evolution of Point Defects in Chip-Level Silicon-Based MOSFET Under Transmission Line Pulse Stress\",\"authors\":\"Xinyuan Zheng;Huiying Li;Yibo Ning;Chengbing Pan;Kai Wang;Lixia Zhao\",\"doi\":\"10.1109/TED.2024.3466840\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this study, the electrical performance and evolution of point defects in chip-level Silicon-based MOSFET under transmission line pulse (TLP) stress were investigated. The experimental results show that the threshold voltage decreased by 9.8%, and the output saturation current increased by 5.9% after the stress. An intrinsic point defect with an energy level of \\n<inline-formula> <tex-math>$0.25~\\\\pm ~0.05$ </tex-math></inline-formula>\\n eV in Si-based MOSFET chips was observed by using deep-level transient spectroscopy (DLTS), which shifted to \\n<inline-formula> <tex-math>$0.37~\\\\pm ~0.05$ </tex-math></inline-formula>\\n eV after the stress. The increase of the trap energy level would reduce the holes at the Si/SiO2 interface, and herein the threshold voltage reduced. This work helps to further understand the evolution of point defects in Si-based MOSFET chips.\",\"PeriodicalId\":13092,\"journal\":{\"name\":\"IEEE Transactions on Electron Devices\",\"volume\":\"71 11\",\"pages\":\"6958-6962\"},\"PeriodicalIF\":2.9000,\"publicationDate\":\"2024-10-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Electron Devices\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10706112/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Electron Devices","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10706112/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Evolution of Point Defects in Chip-Level Silicon-Based MOSFET Under Transmission Line Pulse Stress
In this study, the electrical performance and evolution of point defects in chip-level Silicon-based MOSFET under transmission line pulse (TLP) stress were investigated. The experimental results show that the threshold voltage decreased by 9.8%, and the output saturation current increased by 5.9% after the stress. An intrinsic point defect with an energy level of
$0.25~\pm ~0.05$
eV in Si-based MOSFET chips was observed by using deep-level transient spectroscopy (DLTS), which shifted to
$0.37~\pm ~0.05$
eV after the stress. The increase of the trap energy level would reduce the holes at the Si/SiO2 interface, and herein the threshold voltage reduced. This work helps to further understand the evolution of point defects in Si-based MOSFET chips.
期刊介绍：
IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.
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