高分辨率 SAR ADC 比特权重自校准方法的误差分析

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-19 DOI:10.1109/TVLSI.2024.3458071
Yanhang Chen;Siji Huang;Qifeng Huang;Yifei Fan;Jie Yuan
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引用次数: 0

摘要

高分辨率逐次逼近寄存器(SAR)模数转换器(ADC)通常需要校准位权重。由于校准电路的非理想性,校准后的位权重会产生误差。这种误差可能在校准过程中传播。由于这些 ADC 的精度要求很高,这种残余误差通常会成为整个 ADC 的信噪比 (SNDR) 瓶颈。本文分析了高分辨率 SAR ADC 位权自校准方法产生的残差误差。文章定量分析了造成这一误差的主要来源和减少误差的方法。文章对噪声引起的随机误差进行了统计分析。我们的统计模型发现,噪声引起的随机误差遵循秩方分布。在实践中,这种随机误差通常通过重复测量和平均校准位权来减少。我们的统计模型量化了这种位权重误差,使人们对误差机制和设计权衡有了更清晰的认识。根据我们的秩方模型,校准过程中电路噪声导致的 SNDR 下降可以很容易地估算出来,而无需进行耗时的传统晶体管级设计和仿真过程。所需的重复时间也可以计算出来。本文推导出的位重误差模型在 180-nm CMOS 工艺的 16 位 SAR ADC 设计上进行了测量验证。我们的模型得出的结果与模拟和测量结果十分吻合。
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The Error Analysis of Bit Weight Self-Calibration Methods for High-Resolution SAR ADCs
High-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) commonly need to calibrate their bit weights. Due to the nonidealities of the calibration circuits, the calibrated bit weights carry errors. This error could propagate during the calibration procedure. Due to the high precision requirement of these ADCs, such residue error commonly becomes the signal-to-noise-and-distortion ratio (SNDR) bottleneck of the overall ADC. This article presents an analysis of the residue error from bit weight self-calibration methods of high-resolution SAR ADCs. The major sources contributing to this error and the error reduction methods are quantitively analyzed. A statistical analysis of the noise-induced random error is developed. Our statistical model finds that the noise-induced random error follows the chi-square distribution. In practice, this random error is commonly reduced by repetitively measuring and averaging the calibrated bit weights. Our statistical model quantifies this bit weight error and leads to a clearer understanding of the error mechanism and design trade-offs. Following our chi-square model, the SNDR degradation due to the circuit noise during the calibration can be easily estimated without going through the time-consuming traditional transistor-level design and simulation process. The required repetition time can also be calculated. The bit-weight error models derived in this article are verified with measurement on a 16-bit SAR ADC design in a 180-nm CMOS process. Results from our model match both simulations and measurements well.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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