Xiangdong Wei;Yufan Yue;Seungkyu Choi;Tutu Ajayi;Ronald Dreslinski;David Blaauw;Hun-Seok Kim
{"title":"用于卫星间光学通信的 33.06 Gb/s 可重构伽罗瓦场 oFEC 解码器","authors":"Xiangdong Wei;Yufan Yue;Seungkyu Choi;Tutu Ajayi;Ronald Dreslinski;David Blaauw;Hun-Seok Kim","doi":"10.1109/LSSC.2024.3486234","DOIUrl":null,"url":null,"abstract":"We introduce a high-throughput reconfigurable forward error correction (FEC) decoder capable of decoding BCH, RS, and open FEC (oFEC) codes. With a reconfigurable BCH inner code, the proposed decoder in the oFEC mode provides a wide range of coding gain and throughput to enable efficient and reliable intersatellite optical communication. It features unprecedented reconfigurability for BCH/RS codes in terms of Galois field (GF) size, code length, code rate, and parallel factor, providing tradeoffs between error correction performance, energy, and throughput. Fabricated in 12-nm CMOS technology, the decoder achieves a throughput of 33.06 Gb/s, energy efficiency of 40.35 pJ/b, and a net coding gain of 7.27 dB at \n<inline-formula> <tex-math>$10^{\\text {-6}}$ </tex-math></inline-formula>\n BER with an oFEC code using inner BCH(256, 223).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"331-334"},"PeriodicalIF":2.2000,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 33.06-Gb/s Reconfigurable Galois Field oFEC Decoder for Optical Intersatellite Communication\",\"authors\":\"Xiangdong Wei;Yufan Yue;Seungkyu Choi;Tutu Ajayi;Ronald Dreslinski;David Blaauw;Hun-Seok Kim\",\"doi\":\"10.1109/LSSC.2024.3486234\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We introduce a high-throughput reconfigurable forward error correction (FEC) decoder capable of decoding BCH, RS, and open FEC (oFEC) codes. With a reconfigurable BCH inner code, the proposed decoder in the oFEC mode provides a wide range of coding gain and throughput to enable efficient and reliable intersatellite optical communication. It features unprecedented reconfigurability for BCH/RS codes in terms of Galois field (GF) size, code length, code rate, and parallel factor, providing tradeoffs between error correction performance, energy, and throughput. Fabricated in 12-nm CMOS technology, the decoder achieves a throughput of 33.06 Gb/s, energy efficiency of 40.35 pJ/b, and a net coding gain of 7.27 dB at \\n<inline-formula> <tex-math>$10^{\\\\text {-6}}$ </tex-math></inline-formula>\\n BER with an oFEC code using inner BCH(256, 223).\",\"PeriodicalId\":13032,\"journal\":{\"name\":\"IEEE Solid-State Circuits Letters\",\"volume\":\"7 \",\"pages\":\"331-334\"},\"PeriodicalIF\":2.2000,\"publicationDate\":\"2024-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Solid-State Circuits Letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10734381/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10734381/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
A 33.06-Gb/s Reconfigurable Galois Field oFEC Decoder for Optical Intersatellite Communication
We introduce a high-throughput reconfigurable forward error correction (FEC) decoder capable of decoding BCH, RS, and open FEC (oFEC) codes. With a reconfigurable BCH inner code, the proposed decoder in the oFEC mode provides a wide range of coding gain and throughput to enable efficient and reliable intersatellite optical communication. It features unprecedented reconfigurability for BCH/RS codes in terms of Galois field (GF) size, code length, code rate, and parallel factor, providing tradeoffs between error correction performance, energy, and throughput. Fabricated in 12-nm CMOS technology, the decoder achieves a throughput of 33.06 Gb/s, energy efficiency of 40.35 pJ/b, and a net coding gain of 7.27 dB at
$10^{\text {-6}}$
BER with an oFEC code using inner BCH(256, 223).