DyLaClass:加速 SpMV 时基于动态标签分类的稀疏矩阵格式优化选择

IF 5.6 2区 计算机科学 Q1 COMPUTER SCIENCE, THEORY & METHODS IEEE Transactions on Parallel and Distributed Systems Pub Date : 2024-10-29 DOI:10.1109/TPDS.2024.3488053
Zheng Shi;Yi Zou;Xianfeng Song;Shupeng Li;Fangming Liu;Quan Xue
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引用次数: 0

摘要

稀疏矩阵-矢量乘法(SpMV)在许多科学和工程应用中至关重要,特别是在不同架构下不同稀疏矩阵存储格式的有效性方面,没有一种格式在所有硬件上都表现出色。以往的研究侧重于尝试不同的算法来构建最佳格式的预测器,但却忽略了如何解决最佳格式在同一硬件环境中发生变化的问题,以及如何减少预测开销,而不仅仅是考虑构建预测器的开销。本文基于动态标签和灵活的特征选择,提出了一种优化稀疏矩阵存储格式的新型分类算法 DyLaClass。特别是,我们引入了具有强相关性的混合标签和特征,使我们能够以最小的特征输入实现超高的预测准确率,大大减少了特征提取开销。我们首次提出了 "最合适的存储格式 "而非 "最佳存储格式 "的概念,从而可以在 SpMV 的多次执行中稳定地预测同一矩阵的最佳格式变化。我们还在佛罗里达大学的公共稀疏矩阵收集数据集上进一步演示了所提出的方法。实验结果表明,与现有工作相比,我们的方法达到了高达 91% 的分类准确率。使用两种不同的硬件平台进行验证,所提出的方法比现有方法高出 1.26 到 1.43 倍。最重要的是,提出的预测模型的稳定性比以前的方法高出 25.5%,大大提高了模型在实际现场应用中的可行性。
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DyLaClass: Dynamic Labeling Based Classification for Optimal Sparse Matrix Format Selection in Accelerating SpMV
Sparse matrix-vector multiplication (SpMV) is crucial in many scientific and engineering applications, particularly concerning the effectiveness of different sparse matrix storage formats for various architectures, no single format excels across all hardware. Previous research has focused on trying different algorithms to build predictors for the best format, yet it overlooked how to address the issue of the best format changing in the same hardware environment and how to reduce prediction overhead rather than merely considering the overhead in building predictors. This paper proposes a novel classification algorithm for optimizing sparse matrix storage formats, DyLaClass, based on dynamic labeling and flexible feature selection. Particularly, we introduce mixed labels and features with strong correlations, allowing us to achieve ultra-high prediction accuracy with minimal feature inputs, significantly reducing feature extraction overhead. For the first time, we propose the concept of the most suitable storage format rather than the best storage format, which can stably predict changes in the best format for the same matrix across multiple SpMV executions. We further demonstrate the proposed method on the University of Florida’s public sparse matrix collection dataset. Experimental results show that compared to existing work, our method achieves up to 91% classification accuracy. Using two different hardware platforms for verification, the proposed method outperforms existing methods by 1.26 to 1.43 times. Most importantly, the stability of the proposed prediction model is 25.5% higher than previous methods, greatly increasing the feasibility of the model in practical field applications.
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来源期刊
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems 工程技术-工程:电子与电气
CiteScore
11.00
自引率
9.40%
发文量
281
审稿时长
5.6 months
期刊介绍: IEEE Transactions on Parallel and Distributed Systems (TPDS) is published monthly. It publishes a range of papers, comments on previously published papers, and survey articles that deal with the parallel and distributed systems research areas of current importance to our readers. Particular areas of interest include, but are not limited to: a) Parallel and distributed algorithms, focusing on topics such as: models of computation; numerical, combinatorial, and data-intensive parallel algorithms, scalability of algorithms and data structures for parallel and distributed systems, communication and synchronization protocols, network algorithms, scheduling, and load balancing. b) Applications of parallel and distributed computing, including computational and data-enabled science and engineering, big data applications, parallel crowd sourcing, large-scale social network analysis, management of big data, cloud and grid computing, scientific and biomedical applications, mobile computing, and cyber-physical systems. c) Parallel and distributed architectures, including architectures for instruction-level and thread-level parallelism; design, analysis, implementation, fault resilience and performance measurements of multiple-processor systems; multicore processors, heterogeneous many-core systems; petascale and exascale systems designs; novel big data architectures; special purpose architectures, including graphics processors, signal processors, network processors, media accelerators, and other special purpose processors and accelerators; impact of technology on architecture; network and interconnect architectures; parallel I/O and storage systems; architecture of the memory hierarchy; power-efficient and green computing architectures; dependable architectures; and performance modeling and evaluation. d) Parallel and distributed software, including parallel and multicore programming languages and compilers, runtime systems, operating systems, Internet computing and web services, resource management including green computing, middleware for grids, clouds, and data centers, libraries, performance modeling and evaluation, parallel programming paradigms, and programming environments and tools.
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