{"title":"用于图像处理和神经网络的基于 IMPLY 的高速、高面积效率串行近似减法器和比较器","authors":"Nandit Kaushik;B. Srinivasu","doi":"10.1109/TNANO.2024.3487223","DOIUrl":null,"url":null,"abstract":"In-Memory-Computing (IMC) through memristive architectures has recently gained traction owing to their capacity to perform logic operations within a crossbar, optimizing both area and speed constraints. This paper introduces two approximate serial IMPLY-based subtractor designs, denoted as Serial IMPLY-based Approximate Subtractor Design-1 (SIASD-1), Serial IMPLY-based Approximate Subtractor Design-2 (SIASD-2), with potential applications in image processing and deep neural networks. The proposed designs are implemented in MAGIC topology for comparison, named as Serial MAGIC-based Approximate Subtractor Design-1 (SMASD-1) and Serial MAGIC-based Approximate Subtractor Design-2 (SMASD-2). Moreover, these proposed subtractor designs are extended to design magnitude comparators. IMPLY-based approximate designs improve the overall latency up to 1.67× with energy savings in the range of 17.4% to 40.3% while occupying the same number of memristors for SIASD-1 and an increase of 3 to 5 memristors for SIASD-2, compared to the best existing exact 8-bit serial IMPLY subtractor. SMASD-1 and SMASD-2 improve the latency up to 1.43×, and energy efficiency are up by 77.6% compared to other MAGIC-based exact designs. Additionally, as comparators, the SIASD-1 and SIASD-2 are up to 4.93× faster with energy reduction up to 79.7% compared to their IMPLY-based equivalents. Similarly, the SMASD-1 and SMASD-2 reduce the latency up to 62% with area savings of 77%, compared to MAGIC-based equivalent designs. Furthermore, the proposed subtractor designs undergo analysis in an image processing application called Motion Detection, while the comparators are evaluated in Max Pooling operations. With Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) serving as assessment metrics, the proposed designs consistently demonstrate acceptable PSNR and SSIM values, affirming their suitability for these applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"748-757"},"PeriodicalIF":2.1000,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"High-Speed and Area-Efficient Serial IMPLY-Based Approximate Subtractor and Comparator for Image Processing and Neural Networks\",\"authors\":\"Nandit Kaushik;B. Srinivasu\",\"doi\":\"10.1109/TNANO.2024.3487223\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In-Memory-Computing (IMC) through memristive architectures has recently gained traction owing to their capacity to perform logic operations within a crossbar, optimizing both area and speed constraints. This paper introduces two approximate serial IMPLY-based subtractor designs, denoted as Serial IMPLY-based Approximate Subtractor Design-1 (SIASD-1), Serial IMPLY-based Approximate Subtractor Design-2 (SIASD-2), with potential applications in image processing and deep neural networks. The proposed designs are implemented in MAGIC topology for comparison, named as Serial MAGIC-based Approximate Subtractor Design-1 (SMASD-1) and Serial MAGIC-based Approximate Subtractor Design-2 (SMASD-2). Moreover, these proposed subtractor designs are extended to design magnitude comparators. IMPLY-based approximate designs improve the overall latency up to 1.67× with energy savings in the range of 17.4% to 40.3% while occupying the same number of memristors for SIASD-1 and an increase of 3 to 5 memristors for SIASD-2, compared to the best existing exact 8-bit serial IMPLY subtractor. SMASD-1 and SMASD-2 improve the latency up to 1.43×, and energy efficiency are up by 77.6% compared to other MAGIC-based exact designs. Additionally, as comparators, the SIASD-1 and SIASD-2 are up to 4.93× faster with energy reduction up to 79.7% compared to their IMPLY-based equivalents. Similarly, the SMASD-1 and SMASD-2 reduce the latency up to 62% with area savings of 77%, compared to MAGIC-based equivalent designs. Furthermore, the proposed subtractor designs undergo analysis in an image processing application called Motion Detection, while the comparators are evaluated in Max Pooling operations. With Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) serving as assessment metrics, the proposed designs consistently demonstrate acceptable PSNR and SSIM values, affirming their suitability for these applications.\",\"PeriodicalId\":449,\"journal\":{\"name\":\"IEEE Transactions on Nanotechnology\",\"volume\":\"23 \",\"pages\":\"748-757\"},\"PeriodicalIF\":2.1000,\"publicationDate\":\"2024-10-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Nanotechnology\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10737227/\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Nanotechnology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10737227/","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
High-Speed and Area-Efficient Serial IMPLY-Based Approximate Subtractor and Comparator for Image Processing and Neural Networks
In-Memory-Computing (IMC) through memristive architectures has recently gained traction owing to their capacity to perform logic operations within a crossbar, optimizing both area and speed constraints. This paper introduces two approximate serial IMPLY-based subtractor designs, denoted as Serial IMPLY-based Approximate Subtractor Design-1 (SIASD-1), Serial IMPLY-based Approximate Subtractor Design-2 (SIASD-2), with potential applications in image processing and deep neural networks. The proposed designs are implemented in MAGIC topology for comparison, named as Serial MAGIC-based Approximate Subtractor Design-1 (SMASD-1) and Serial MAGIC-based Approximate Subtractor Design-2 (SMASD-2). Moreover, these proposed subtractor designs are extended to design magnitude comparators. IMPLY-based approximate designs improve the overall latency up to 1.67× with energy savings in the range of 17.4% to 40.3% while occupying the same number of memristors for SIASD-1 and an increase of 3 to 5 memristors for SIASD-2, compared to the best existing exact 8-bit serial IMPLY subtractor. SMASD-1 and SMASD-2 improve the latency up to 1.43×, and energy efficiency are up by 77.6% compared to other MAGIC-based exact designs. Additionally, as comparators, the SIASD-1 and SIASD-2 are up to 4.93× faster with energy reduction up to 79.7% compared to their IMPLY-based equivalents. Similarly, the SMASD-1 and SMASD-2 reduce the latency up to 62% with area savings of 77%, compared to MAGIC-based equivalent designs. Furthermore, the proposed subtractor designs undergo analysis in an image processing application called Motion Detection, while the comparators are evaluated in Max Pooling operations. With Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) serving as assessment metrics, the proposed designs consistently demonstrate acceptable PSNR and SSIM values, affirming their suitability for these applications.
期刊介绍:
The IEEE Transactions on Nanotechnology is devoted to the publication of manuscripts of archival value in the general area of nanotechnology, which is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.