Analysis of MOS capacitor with p layer with TCAD simulation

The ATLAS18 strip sensors of the ATLAS inner tracker upgrade (ITk) are in production since 2021. Along with the large-format n${}^{+}$-in-p strip sensor in the center of 6-inch wafer, test structures including Metal–Oxide–Silicon (MOS) capacitors are laid out in the open space for monitoring the performance of the strip sensor and its fabrication process. One of the MOS capacitors is with a p-implantation in the surface of silicon to access the p-stop doping for isolating the n${}^{+}$ strips, the MOS-p capacitor. The capacitance measurement of the standard MOS capacitor as a function of gate voltage (C–V) shows characteristic behavior in the accumulation, depletion, and inversion regimes, from which one can deduce the amount of the interface charge. The MOS-p capacitor shows the C–V characteristics modulated by the properties of the p-layer. With over 50% of the full production complement delivered, we have observed consistent characteristics in the MOS-p capacitors. Rarely and currently only in three incidents, we have observed anomalous behaviors which implied lower density of p-layer. To study the cause, we have simulated the MOS-p capacitor with a TCAD device simulator. The normal characteristic curve is reproduced successfully with p-density and interface charge within the expected ranges, including a feature caused by a geometrical offset. The anomalous C–V characteristics cannot be explained simply by low p-density, but instead explained with the p-layer density near the specification which goes to zero at the surface. The loss of density could have been introduced with an n-type surface contamination or some other effect such as “dopant segregation”. These simulations have helped to take final acceptance decisions for the batches in production.