使用基于杉木作为环路滤波器的 ADPLL 的 TRNG 架构的 FPGA 设计与实现

IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Analog Integrated Circuits and Signal Processing Pub Date : 2024-11-27 DOI:10.1007/s10470-024-02295-8
Huirem Bharat Meitei, Manoj Kumar
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引用次数: 0

摘要

本文全面介绍了真随机数发生器(TRNG)的设计、实现和分析。TRNG 采用全数字锁相环 (ADPLL),并将有限脉冲响应 (FIR) 滤波器作为数字环路滤波器。TRNG 利用 Xilinx Vivado v.2015.2 设计套件在 Artix 7 (XC7A35T-CPG236-1) FPGA 板上实现。三阶广播低通数字 FIR 滤波器的系数计算是通过 Keiser 窗口技术进行的。滤波器系数的计算使用了 MATLAB 滤波器设计和分析工具。在应用 XOR-校正器后处理方法减轻序列中的偏差后,基于 ADPLL 的 TRNG 的拟议设计成功生成了无偏随机数。这些设计在两种配置下均实现了 200 Mbps 的总体吞吐量。最初提出的基于有限脉冲响应全数字锁相环(FIR-ADPLL)的 TRNG 设计(称为 FAT-1)功耗为 0.072 W。Artrix-7 现场可编程门阵列板用于与 DSO 建立连接,以捕捉 TRNG 产生的波形。这两种基于 FIR 的全数字锁相环真随机数发生器的建议设计都成功通过了 NIST SP 800-22 标准的测试。这表明这些设计与网络安全、网络安全、银行安全、智能卡、RFID 标签、物联网和工业物联网等广泛的工业应用具有很强的兼容性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

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FPGA design and implementation of TRNG architecture using ADPLL based on fir as loop filter

This article presents a comprehensive examination of the design, implementation, as well as analysis of a true random number generator (TRNG). The TRNG utilizes an all-digital phase-locked loop (ADPLL) that incorporates a finite impulse response (FIR) filter as the digital loop filter. The TRNG is implemented on the Artix 7 (XC7A35T-CPG236-1) FPGA board, leveraging the Xilinx Vivado v.2015.2 design suite. The computation of the coefficients for a third-order broadcast low pass digital FIR filter is performed via the Keiser window technique. The MATLAB filter design and analysis tool is utilized for the computation of filter coefficients. Following the application of the XOR-corrector post-processing method to mitigate bias in the sequence, the proposed designs of ADPLL-based TRNGs successfully generated an unbiased stochastic random number. These designs achieved an overall throughput of 200 Mbps for both configurations. The initial proposed design for a TRNG based on a Finite Impulse response-all-digital phase-locked loop (FIR-ADPLL), referred to as FAT-1, exhibits a power consumption of 0.072 W. In contrast, the subsequent proposed TRNG design, also based on a FIR-ADPLL, known as FAT-2, demonstrates a slightly higher power consumption of 0.074 W. The bitstream that is obtained is assessed for randomness through the application of the NIST test, which is conducted after post-processing. The Artrix-7 field-programmable gate array board is utilized to establish a connection with the DSO for the purpose of capturing the waveforms produced by the TRNG. Both of the suggested designs for FIR-based all-digital phase-locked loop true random number generators successfully underwent testing according to the NIST SP 800-22 standard. This indicates that these designs exhibit strong compatibility with a wide range of industrial applications, such as network security, cybersecurity, banking security, smart cards, RFID tags, the internet of things, and industrial internet of things.

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来源期刊
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing 工程技术-工程:电子与电气
CiteScore
0.30
自引率
7.10%
发文量
141
审稿时长
7.3 months
期刊介绍: Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today. A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.
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