A Dynamic Capacitance Matching (DCM)-Based Current Response Algorithm for Signal Line RC Network

This paper proposes a dynamic capacitance matching (DCM)-based RC current response algorithm for calculating the current waveform of a signal line without performing transistor level SPICE simulation. Specifically, unlike previous methods such as current source model, driver linear representation, waveform functional fitting or equivalent load capacitance, our algorithm does not rely on fixed reduced model of standard-cell driver or RC load. Instead, it approaches the current waveform dynamically by computing current responses of the target driver for various load scenarios. Besides, we creatively use symbolic expression to combine the y-parameter of RC network with the pre-characterized driver library in order to perform capacitance matching and simulate current waveform by considering the Miller and over/undershoot effects. Our algorithm is experimentally verified on 40nm CMOS technology and has been adopted by latest commercial tool for different nodes (from 180nm to 3nm). Experimental results show that our algorithm has only about 1% error compared with SPICE golden results while the runtime is improved by 50 to 200 times, which demonstrates overwhelming capability in calculating timing, power and electromigration of signal lines.