GCStack:一个GPU周期核算机制,提供准确的GPU性能洞察

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2024-10-09 DOI:10.1109/LCA.2024.3476909
Hanna Cha;Sungchul Lee;Yeonan Ha;Hanhwi Jang;Joonsung Kim;Youngsok Kim
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引用次数: 0

摘要

每指令周期(CPI)堆栈帮助计算机架构师深入了解其目标体系结构和应用程序的性能。为了将CPI堆栈的好处带给图形处理单元(GPU),先前的研究已经提出了GPU周期会计机制,可以识别GPU架构上的失速周期及其失速事件。不幸的是,由于其粗粒度、优先级驱动和以问题为中心的周期会计机制,先前的研究无法提供对GPU性能的准确洞察。在这封信中,我们提出了GCStack,这是一种细粒度的GPU周期会计机制,可以构建准确的CPI堆栈并准确识别主要GPU性能瓶颈。GCStack首先公开经纱调度器中所有未完成的经纱的失速事件,其中大部分被现有机制隐藏。然后,GCStack将结构失速的分类推迟到GPU管道的后期阶段,现有机制无法正确识别其以问题阶段为中心的失速分类。我们在Accel-Sim上实现了GCStack,并表明GCStack提供了比GSI更准确的CPI堆栈和GPU性能洞察,GSI是最先进的GPU周期会计机制,其主要重点是表征与内存相关的延迟。
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GCStack: A GPU Cycle Accounting Mechanism for Providing Accurate Insight Into GPU Performance
Cycles Per Instruction (CPI) stacks help computer architects gain insight into the performance of their target architectures and applications. To bring the benefits of CPI stacks to Graphics Processing Units (GPUs), prior studies have proposed GPU cycle accounting mechanisms that can identify the stall cycles and their stall events on GPU architectures. Unfortunately, the prior studies cannot provide accurate insight into the GPU performance due to their coarse-grained, priority-driven, and issue-centric cycle accounting mechanisms. In this letter, we present GCStack , a fine-grained GPU cycle accounting mechanism that constructs accurate CPI stacks and accurately identifies primary GPU performance bottlenecks. GCStack first exposes all the stall events of the outstanding warps of a warp scheduler, most of which get hidden by the existing mechanisms. Then, GCStack defers the classification of structural stalls, which the existing mechanisms cannot correctly identify with their issue-stage-centric stall classification, to the later stages of the GPU pipeline. We implement GCStack on Accel-Sim and show that GCStack provides more accurate CPI stacks and GPU performance insight than GSI, the state-of-the-art GPU cycle accounting mechanism whose primary focus is on characterizing memory-related stalls.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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