基于系统技术协同优化的晶片集成过程中应力对FinFET交流和直流量子输运影响的多物理场模拟

IF 2.9 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Electron Devices Pub Date : 2024-11-20 DOI:10.1109/TED.2024.3488676
Liang Tian;Yizhang Liu;Wenchao Chen
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引用次数: 0

摘要

混合键合以其更高的互连密度、更低的功耗和更好的信号完整性等独特优势,在先进的2.5 d /3-D芯片集成中发挥着重要作用。然而,杂化键合的退火和冷却过程中产生的应变会影响芯片中逻辑器件的直流/交流性能。本文基于非平衡格林函数(NEGF)形式,将杂化键合过程中的应力引入到FinFET的量子输运模拟中,进行了耦合多物理场模拟,研究了杂化键合过程对p型FinFET性能的影响。其中,利用六波段${k} \cdot {p}$哈密顿量和变形势理论,捕捉了杂化键合过程引起的应力对器件能带结构的影响。仿真结果表明,杂化键合过程诱导应力引起的态密度(DOSs)变化可以提高通道内的导通电流和空穴密度,并探讨了过程诱导应力对Y参数和栅极电容频域的影响。靠近铜柱中心的设备比远离铜柱的设备受影响更大。减小铜柱半径和退火温度或增大铜柱之间的距离可以减小FinFET中杂化键合过程引起的应力,从而减小器件性能的变化,包括导通电流、Y参数和栅极电容。
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Multiphysics Simulation of Chiplet Integration Process-Induced Stress Effects on AC and DC Quantum Transport of FinFET From System Technology Co-Optimization Perspective
Hybrid bonding plays an important role in advanced 2.5-D/3-D chiplet integration due to its distinctive advantages, such as higher interconnect density, lower power consumption, and better signal integrity. However, the dc/ac performance of the logic device in chiplet can be affected by the strain induced by the annealing and cooling steps of hybrid bonding. In this article, a coupled multiphysics simulation is performed to investigate the impact of the hybrid bonding process on the performance of p-type FinFET by introducing stress from the hybrid bonding process into quantum transport simulation for FinFET based on nonequilibrium Green’s function (NEGF) formalism, in which the impact of hybrid bonding process-induced stress on the band structure of the device is captured by employing six-band ${k} \cdot {p}$ Hamiltonian and deformation potential theory. The simulation results indicate that the on-state current and the hole density in the channel can be enhanced due to the variation of the density of states (DOSs) caused by hybrid bonding process-induced stress, the effect of process-induced stress on Y parameters and gate capacitance in the frequency domain is also explored. Devices near the center of copper pillars are more affected than those far away from the copper pillars. Decreasing the radius of copper pillars and annealing temperature or increasing the distance between copper pillars can decrease the hybrid bonding process-induced stress in FinFET, hence decreasing the change in device performance, including on -state current, Y parameters, and gate capacitance.
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来源期刊
IEEE Transactions on Electron Devices
IEEE Transactions on Electron Devices 工程技术-工程:电子与电气
CiteScore
5.80
自引率
16.10%
发文量
937
审稿时长
3.8 months
期刊介绍: IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.
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