拼写:一个端到端的工具流程为llm引导的安全SoC设计的嵌入式系统

IF 1.7 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Embedded Systems Letters Pub Date : 2024-12-05 DOI:10.1109/LES.2024.3447691
Sudipta Paria;Aritra Dasgupta;Swarup Bhunia
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引用次数: 0

摘要

现代嵌入式系统和物联网(IoT)设备包含片上系统(soc)作为其硬件骨干,其中越来越多地包含许多关键资产(安全通信密钥,配置位,固件,敏感数据等)。必须保护这些关键资产免受各种潜在漏洞的侵害,以维护系统的机密性、完整性和可用性。如今的SoC设计包含多种知识产权(IP)模块,通常是从多个第三方IP供应商那里获得的。使用它们的安全硬件设计不可避免地依赖于训练有素的安全专家积累的领域知识。在这封信中,我们介绍了SPELL,这是一种用于安全SoC设计自动化开发的新型端到端框架。它利用会话式大型语言模型(llm)自动识别目标SoC中的安全漏洞,并将其映射到不断发展的常见弱点枚举(CWEs)数据库;然后,SPELL过滤相关的CWEs,随后将它们转换为系统verilog断言(SVAs)进行验证;最后,通过集中的安全策略实施来解决漏洞。我们已经使用流行的llm(如ChatGPT和GEMINI)实现了SPELL框架,以分析它们在从用户定义的SoC规范生成适当的CWEs方面的功效,并为开源SoC基准实现相应的安全策略。在这种情况下,我们还探讨了现有的预训练会话法学硕士的局限性。
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SPELL: An End-to-End Tool Flow for LLM-Guided Secure SoC Design for Embedded Systems
Modern embedded systems and Internet of Things (IoT) devices contain system-on-chips (SoCs) as their hardware backbone, which increasingly contain many critical assets (secure communication keys, configuration bits, firmware, sensitive data, etc.). These critical assets must be protected against wide array of potential vulnerabilities to uphold the system’s confidentiality, integrity, and availability. Today’s SoC designs contain diverse intellectual property (IP) blocks, often acquired from multiple 3rd-party IP vendors. Secure hardware design using them inevitably relies on the accrued domain knowledge of well-trained security experts. In this letter, we introduce SPELL , a novel end-to-end framework for the automated development of secure SoC designs. It leverages conversational large language models (LLMs) to automatically identify security vulnerabilities in a target SoC and map them to the evolving database of common weakness enumerations (CWEs); SPELL then filters the relevant CWEs, subsequently converting them to systemverilog assertions (SVAs) for verification; and finally, addresses the vulnerabilities via centralized security policy enforcement. We have implemented the SPELL framework using popular LLMs, such as ChatGPT and GEMINI, to analyze their efficacy in generating appropriate CWEs from user-defined SoC specifications and implement corresponding security policies for an open-source SoC benchmark. We have also explored the limitations of existing pretrained conversational LLMs in this context.
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来源期刊
IEEE Embedded Systems Letters
IEEE Embedded Systems Letters Engineering-Control and Systems Engineering
CiteScore
3.30
自引率
0.00%
发文量
65
期刊介绍: The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software. The emphasis is on models, methods, and tools that ensure secure, correct, efficient and robust design of embedded systems and their applications.
期刊最新文献
Table of Contents Editorial IEEE Embedded Systems Letters Publication Information ViTSen: Bridging Vision Transformers and Edge Computing With Advanced In/Near-Sensor Processing Methodology for Formal Verification of Hardware Safety Strategies Using SMT
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