通过乐观路径实现低延迟dag的BFT

IF 3.6 2区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Computers Pub Date : 2024-09-16 DOI:10.1109/TC.2024.3461309
Xiaohai Dai;Wei Li;Guanxiong Wang;Jiang Xiao;Haoyang Chen;Shufei Li;Albert Y. Zomaya;Hai Jin
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引用次数: 0

摘要

作为区块链系统的基础元素,拜占庭容错(BFT)共识在过去十年中获得了极大的关注。在BFT共识设计中引入有向无环有向(DAG)结构,称为基于DAG的BFT,已经出现以提高吞吐量。然而,流行的基于dag的协议与大量的延迟问题作斗争,与非dag协议相比,存在延迟差距。例如,名为GradedDAG和BullShark的基于dag的前沿协议分别表现出4美元和6美元的良好情况延迟。相比之下,以PBFT为例的非dag协议在有利条件下的延迟为3美元。为了弥补这种延迟差距,我们提出了一种新的基于dag的BFT协议Remora。通过整合乐观路径,《Remora》实现了3美元回合的延迟减少。在其核心,remoa努力通过乐观路径提交区块,在有利的情况下促进低延迟。相反,在不利的情况下,䲟鱼无缝过渡到悲观的路径,以确保生存。各种实验验证了rema的可行性和效率,突出了其作为BFT共识协议领域强大解决方案的潜力。
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Remora: A Low-Latency DAG-Based BFT Through Optimistic Paths
Standing as a foundational element within blockchain systems, the Byzantine Fault Tolerant (BFT) consensus has garnered significant attention over the past decade. The introduction of a Directed Acyclic Directed (DAG) structure into BFT consensus design, termed DAG-based BFT, has emerged to bolster throughput. However, prevalent DAG-based protocols grapple with substantial latency issues, suffering from a latency gap compared to non-DAG protocols. For instance, leading-edge DAG-based protocols named GradedDAG and BullShark exhibit a good-case latency of $4$ and $6$ communication rounds, respectively. In contrast, the non-DAG protocol, exemplified by PBFT, attains a latency of $3$ rounds in favorable conditions. To bridge this latency gap, we propose Remora, a novel DAG-based BFT protocol. Remora achieves a reduced latency of $3$ rounds by incorporating optimistic paths. At its core, Remora endeavors to commit blocks through the optimistic path initially, facilitating low latency in favorable situations. Conversely, in unfavorable scenarios, Remora seamlessly transitions to a pessimistic path to ensure liveness. Various experiments validate Remora's feasibility and efficiency, highlighting its potential as a robust solution in the realm of BFT consensus protocols.
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来源期刊
IEEE Transactions on Computers
IEEE Transactions on Computers 工程技术-工程:电子与电气
CiteScore
6.60
自引率
5.40%
发文量
199
审稿时长
6.0 months
期刊介绍: The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field. It publishes papers on research in areas of current interest to the readers. These areas include, but are not limited to, the following: a) computer organizations and architectures; b) operating systems, software systems, and communication protocols; c) real-time systems and embedded systems; d) digital devices, computer components, and interconnection networks; e) specification, design, prototyping, and testing methods and tools; f) performance, fault tolerance, reliability, security, and testability; g) case studies and experimental and theoretical evaluations; and h) new and important applications and trends.
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