{"title":"具有1/4 dtc范围缩减技术的低抖动分数n lc -锁相环","authors":"Gaofeng Jin;Fei Feng;Yan Chen;Hanli Liu;Xiang Gao","doi":"10.1109/LSSC.2025.3528005","DOIUrl":null,"url":null,"abstract":"A fractional-N LC oscillator-based phase-locked loop (PLL) with a 1/4 quantization noise (QN) range reduction technique is proposed. Simple open-loop delay cells are used to generate 4-phase clocks and reduce the QN by a factor of 4 while the mismatches of the four phases are calibrated and covered by a single DTC. Designed in 40-nm CMOS process, the proposed PLL achieves 159-fs RMS-jitter with 2.6-mW power consumption, leading to –251.8-dB FoM.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"45-48"},"PeriodicalIF":2.0000,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique\",\"authors\":\"Gaofeng Jin;Fei Feng;Yan Chen;Hanli Liu;Xiang Gao\",\"doi\":\"10.1109/LSSC.2025.3528005\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fractional-N LC oscillator-based phase-locked loop (PLL) with a 1/4 quantization noise (QN) range reduction technique is proposed. Simple open-loop delay cells are used to generate 4-phase clocks and reduce the QN by a factor of 4 while the mismatches of the four phases are calibrated and covered by a single DTC. Designed in 40-nm CMOS process, the proposed PLL achieves 159-fs RMS-jitter with 2.6-mW power consumption, leading to –251.8-dB FoM.\",\"PeriodicalId\":13032,\"journal\":{\"name\":\"IEEE Solid-State Circuits Letters\",\"volume\":\"8 \",\"pages\":\"45-48\"},\"PeriodicalIF\":2.0000,\"publicationDate\":\"2025-01-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Solid-State Circuits Letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10836930/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10836930/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique
A fractional-N LC oscillator-based phase-locked loop (PLL) with a 1/4 quantization noise (QN) range reduction technique is proposed. Simple open-loop delay cells are used to generate 4-phase clocks and reduce the QN by a factor of 4 while the mismatches of the four phases are calibrated and covered by a single DTC. Designed in 40-nm CMOS process, the proposed PLL achieves 159-fs RMS-jitter with 2.6-mW power consumption, leading to –251.8-dB FoM.
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