A 28-nm 8-Bit 16-GS/ DAC With >60 dBc/>40 dBc SFDR Up To 2.3 GHz/5.4 GHz Using 4-Channel NRZ-Output-Overlapped Time-Interleaving

This brief validates in silicon a four-channel non-return-to-zero (NRZ) output-overlapped (OO) time-interleaving (TI) digital-to-analog converter (DAC) for the first time. The proposed 4-ch TI DAC achieves a sampling rate (Fs) of 16-GS/s, with each sub-DAC operating at a speed of only Fs/4. Compared with conventional RZ structures, the proposed structure uses fewer clocks and avoids the use of high-speed clocks. Additionally, the output-overlapping design reduces DAC’s sensitivity to duty-cycle mismatches. The DAC was fabricated in 28nm CMOS, incorporating a low-complexity phase error correction (PEC) unit to ensure precise phase alignment for the sub-DACs. Experimental results demonstrate that this DAC achieves a spurious-free dynamic range (SFDR) of >60dBc (>40dBc) up to 2.3GHz (5.4GHz), representing a significant advancement over the state-of-the-art solutions within the 2.3GHz frequency range of interest.