ARS-Flow 2.0:基于主动学习的富加速器系统的增强设计空间探索流程

IF 2.5 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Integration-The Vlsi Journal Pub Date : 2025-03-01 Epub Date: 2024-12-14 DOI:10.1016/j.vlsi.2024.102315
Shuaibo Huang, Yuyang Ye, Hao Yan, Longxing Shi
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引用次数: 0

摘要

基于代理模型的设计空间探索(DSE)是搜索最优微架构设计的主流方法。然而,由于它们的高维性,在有限的样本中为富含加速器的系统建立精确的模型是具有挑战性的。此外,这些模型经常陷入局部最优或难以收敛。为了解决这些问题,我们提出了一种基于主动学习的DSE流程,称为ARS-Flow。该方法采用粒子群优化高斯过程回归模型(PSOGPR)、自适应超参数控制多目标遗传算法(SAMOGA)和面向pareto区域的随机重采样方法(PRSRS)。使用gem5-SALAM系统进行评估,该方法可以建立更精确的模型,并在可接受的运行成本下找到更好的微架构设计。
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ARS-Flow 2.0: An enhanced design space exploration flow for accelerator-rich system based on active learning
Surrogate model-based design space exploration (DSE) is the mainstream method to search for optimal microarchitecture designs. However, building accurate models for accelerator-rich systems within limited samples is challenging due to their high dimensionality. Additionally, these models often fall into local optima or have difficulty converging. To address these issues, we propose a DSE flow based on active learning, called ARS-Flow. This method features particle-swarm-optimized Gaussian process regression modeling (PSOGPR), a multiobjective genetic algorithm with self-adaptive hyperparameter control (SAMOGA), and a Pareto-region-oriented stochastic resampling method (PRSRS). Using the gem5-SALAM system for evaluation, the proposed method can build more accurate models and find better microarchitecture designs with acceptable runtime costs.
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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