High-performance CORDIC-based approximate MAC architectures for FPGA platforms

CORDIC is a versatile algorithm frequently used in different signal-processing operations. While using CORDIC-based computations in evaluating trigonometric and transcendental functions is quite prevalent, the resource overhead associated with its implementation does not justify its use in evaluating linear functions like multiplication and addition. However, with the emergence of approximate computing as an attractive paradigm for error-resilient applications, the algorithm can be used to design approximate linear computational units that completely justify the accuracy-performance trade-offs. In this paper, we model the CORDIC-based computations to emulate the multiply-accumulate operation, albeit with some loss of accuracy. We specifically present two incremental CORDIC-based multiply-accumulate architectures with an attempt to improve the accuracy-performance trade-offs with each increment. A detailed Pareto analysis for 8 and 16-bit unsigned and signed multiply-accumulate structures is conducted to determine the optimum number of computing stages and the associated bit-precision of the intermediate results. Accuracy and performance analysis using 6th and 7th generation FPGAs reveals a substantial improvement over state-of-the-art designs. The proposed architectures are also tested using three image processing applications, and the output results are promising.