Optimization of interface properties in p-type poly-SiOx passivating contacts through intrinsic buffer layer modification

Polycrystalline silicon (poly-Si) carrier-selective passivating contacts (CSPCs), featuring high photoconversion efficiency (PCE) and cost-effectiveness, have emerged as a promising approach for high-efficiency crystalline silicon (c-Si) solar cells. To minimize parasitic absorption losses induced by doped poly-Si window layers, wide bandgap oxygen-alloyed poly-Si (poly-SiO_x) layers are developed. However, challenges persist in achieving excellent surface passivation for boron-doped poly-SiO_x contact stacks, likely caused by boron diffusion during annealing and the reduced doping concentration resulting from lower crystallinity as oxygen content increases. In this study, we investigate the impact on the passivating contact structure and solar cell performance of a 10-nm thick intrinsic hydrogenated amorphous silicon buffer layer with varying oxygen content (a-Si (O_x):H) deposited by plasma-enhanced chemical vapor deposition (PECVD), and placed between the tunneling silicon oxide (SiO_x) and the poly-SiO_x (p⁺). After the hydrogenation step, we obtain both high passivation quality with implied open circuit voltage (iV_oc) of 728.3 mV and low contact resistivity (ρ_c) of 59.18 mΩ cm² on polished surface for oxygen-free a-Si:H buffer layer. These improvements can be attributed to the appropriate thickness of the tunnel oxide and confirmed by transmission electron microscopy (TEM) images, to higher crystallinity of the buffer layer, which facilitates more efficient doping in the buffer layer. This is evidenced by energy dispersive X-ray spectroscopy (EDX), and X-ray photoelectron spectroscopy (XPS) results. At the device level, a front-side textured, rear-side flat, rear junction poly-SiO_x/poly-SiO_x solar cell on n-type c-Si wafer, an efficiency improvement can be observed from 3.55 % without a PECVD buffer layer to 18.9 % with an oxygen-free a-Si:H PECVD buffer layer. The impact of the buffer layer crystallinity on cell performance is further demonstrated by deploying a 10-nm thick LPCVD buffer layer, which facilitates an efficiency of 21.15 % for the same device structure.