IF 5.2 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-24 DOI:10.1109/TCSI.2024.3461736
Yan Xu;Lin Ding;Penggao He;Zhaojun Lu;Jiliang Zhang
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引用次数: 0

摘要

多项式乘法(PM)是后量子密码学(PQC)等基于网格的密码学的计算瓶颈。为多项式乘法设计专用硬件加速器是提高执行速度的有效解决方案。然而,目前的主流设计忽略了计算阵列大小的影响,导致设计灵活性差、内存利用率低。为了解决这些问题,我们提出了具有内存效率的三级 PM 加速器 Meta。我们提出的三阶段 PM 算法将所有孤立的子阶段融合到一个名为 "融合系数乘法(FCWM)"的独特阶段中,确保了高效计算。同时,在算法的不同阶段,对二维可重构耦合蝶形单元(2D-RCBFUs)电路进行细粒度重构,以提高资源利用率。此外,低复杂度内存映射方案简化了地址控制逻辑,降低了硬件开销。Meta 可以高效地支持任意 2 次幂的 PM,这是以前使用二维计算阵列的设计所无法实现的。与最先进的设计相比,我们的Meta展示了最佳的内存利用率,实现了高达10.0倍的性能提升。
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Meta: A Memory-Efficient Tri-Stage Polynomial Multiplication Accelerator Using 2D Coupled-BFUs
Polynomial multiplication (PM) is the computational bottleneck of lattice-based cryptography, such as post-quantum cryptography (PQC). Designing dedicated hardware accelerators for polynomial multiplication is an effective solution to improve the execution speed. However, current mainstream designs ignore the impact of computing array size, resulting in poor design flexibility and low memory utilization. To address these issues, we propose Meta, a memory-efficient tri-stage PM accelerator. Our proposed tri-stage PM algorithm fuses all isolated substages into a unique stage named fused coefficient-wise multiplication (FCWM), ensuring efficient computation. Meanwhile, in different stages of the algorithm, the circuit of two-dimensional reconfigurable coupled butterfly units (2D-RCBFUs) is fine-grained reconfigured to improve resource utilization. Moreover, the low-complexity memory mapping scheme simplifies the address control logic and reduces the hardware overhead. Meta can efficiently support the PM of an arbitrary power of two, which is impossible for previous designs using a 2D computing array. Compared with the state-of-the-art designs, our Meta demonstrates the best memory utilization, achieving up to $10.0\times $ performance improvement.
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来源期刊
IEEE Transactions on Circuits and Systems I: Regular Papers
IEEE Transactions on Circuits and Systems I: Regular Papers 工程技术-工程:电子与电气
CiteScore
9.80
自引率
11.80%
发文量
441
审稿时长
2 months
期刊介绍: TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.
期刊最新文献
Table of Contents IEEE Circuits and Systems Society Information IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information Guest Editorial Special Issue on Emerging Hardware Security and Trust Technologies—AsianHOST 2023
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