时间交错SAR adc通道间偏移失配的实时旋转校正

IF 3.1 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-16 DOI:10.1109/TVLSI.2024.3472095
Yixiao Luo;Hongzhi Liang;Zeyu Peng;Yukui Yu;Shubin Liu;Ruixue Ding;Zhangming Zhu
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引用次数: 0

摘要

本文介绍了一种片上实时旋转校准(RRC)技术,旨在缓解时间交错(TI)逐次逼近寄存器模数转换器(SAR ADC)中的通道间偏移失配。通过利用模拟域的自旋转校准和自补偿策略,该技术在PVT变化中表现出鲁棒性。两个额外的子通道涉及到TI量化机制,其中采样时钟分布的连续旋转确保它们在校准模式下运行。为了验证所提出的校准的有效性,在28纳米工艺中设计并实现了一个8 × 8 bit的8 GS/s TI-SAR ADC,其有效面积为0.273 mm2,每个子通道SAR ADC仅覆盖86 × 23~ $ mu $ m。大量的仿真结果验证了RRC的有效性,显示出动态性能的显着改善。具体来说,在奈奎斯特输入频率下,SNDR从37.1增加到45.4 dB, SFDR从57.8增加到60.7 dB。
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A Real-Time Rotation Calibration for Interchannel Offset Mismatch in Time-Interleaved SAR ADCs
This brief presents an on-chip, real-time rotation calibration (RRC) technique aimed at alleviating the inter-channel offset mismatch in time-interleaved (TI) successive-approximation register analog-to-digital converter (SAR ADC). By leveraging auto-rotation calibration and self-compensation strategies in the analog domain, the proposed technique demonstrates robust performance across PVT variations. Two additional sub-channels are involved in the TI quantization mechanism, where the continuous rotation of the sampling clock distribution ensures their operation in calibration mode. To validate the effectiveness of the proposed calibration, an $8\times 8$ bit 8 GS/s TI-SAR ADC is designed and implemented in a 28-nm process and occupies an active area of 0.273 mm2, with each sub-channel SAR ADC covering only $86\times 23~\mu $ m. Extensive simulation results validate the efficacy of RRC, demonstrating significant improvements in dynamic performance. Specifically, SNDR increases from 37.1 to 45.4 dB, while SFDR rises from 57.8 to 60.7 dB, as observed at the Nyquist input frequency.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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