Impact of Physical Stress on Gate Dielectric in Ultrathin Si Gate-Stack for Next-Generation Flexible CMOS Technology

In this article, we report the fabrication and characterizations of sub-20- $\mu $ m thin flexible Si die containing active devices. Thermally grown 2.62-nm silicon dioxide (SiO2), atomic layer deposition (ALD)-deposited 3-nm HfO2 (high- $\kappa $ ), and 10-nm TiN layers are used to fabricate an array of MOSCAPs on Si wafers. The fabricated devices are characterized to analyze the doping density ( ${N} _{a}$ ), flat-band voltage ( ${V} _{\text {fb}}$ ), threshold voltage ( ${V} _{\text {th}}$ ), fixed oxide charge ( ${Q} _{f}$ ), and interface trap densities ( ${D} _{\text {it}}$ ). Then, a deep reactive ion etching (DRIE) reduces the die thickness to $\sim 15\mu $ m for flexibility. The encapsulated flexible devices are found to have relatively better breakdown performances when tested in compressive stressing and no variations when in tensile stress. The time-dependent dielectric breakdown (TDDB) measurement shows a minimal variation in flexible and bulk devices. The TDDB and a voltage acceleration slope are projected in flexible devices after performing a 10000 times bending and relaxation process (cycling).