{"title":"通过粘结多孔铜凸块和超薄铜/锰焊盘实现低电阻互连器件","authors":"Zilin Wang;Wenjie Zhao;Zheyao Wang","doi":"10.1109/TED.2025.3530867","DOIUrl":null,"url":null,"abstract":"CuSn-Cu bonding is widely used in 2.5-D integration due to the ease of operation. However, it suffers from high bond resistance due to the high resistivity of Cu-Sn intermetallic compounds (IMCs) and the high contact resistance due to the Kirkendall voids at the Cu/IMC interfaces. We report a low-resistance CuSn-Cu interconnect fabricated by bonding a porous Cu bump and a Cu-Sn pad with a 200-nm Sn layer. The porous Cu bump, fabricated by treating normal Cu-Sn bumps with oxygen and formic acid, is bonded with the Cu-Sn pad through solid-state bonding at 100 °C under a 5-MPa pressure, followed by 250 °C annealing. The bonding pressure presses the porous Cu to distribute uniformly into the Sn layer, avoiding the Kirkendall voids by providing the Cu atoms locally instead of all from the Cu/Sn interfaces for Cu-Sn reactions. The IMC resistance is also reduced as the 200-nm Sn layer forms an ultrathin IMC layer. A large-scale bump array has been bonded successfully, and a single bond resistance of 6.5 m<inline-formula> <tex-math>$\\Omega $ </tex-math></inline-formula> and a specific contact resistivity (SCR) of <inline-formula> <tex-math>$1.0\\times 10^{-}9 ~\\Omega \\cdot $ </tex-math></inline-formula> cm2 have been obtained.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1276-1281"},"PeriodicalIF":2.9000,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Low-Resistance Interconnects by Bonding Porous Cu Bumps and Ultrathin Cu/Sn Pads\",\"authors\":\"Zilin Wang;Wenjie Zhao;Zheyao Wang\",\"doi\":\"10.1109/TED.2025.3530867\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"CuSn-Cu bonding is widely used in 2.5-D integration due to the ease of operation. However, it suffers from high bond resistance due to the high resistivity of Cu-Sn intermetallic compounds (IMCs) and the high contact resistance due to the Kirkendall voids at the Cu/IMC interfaces. We report a low-resistance CuSn-Cu interconnect fabricated by bonding a porous Cu bump and a Cu-Sn pad with a 200-nm Sn layer. The porous Cu bump, fabricated by treating normal Cu-Sn bumps with oxygen and formic acid, is bonded with the Cu-Sn pad through solid-state bonding at 100 °C under a 5-MPa pressure, followed by 250 °C annealing. The bonding pressure presses the porous Cu to distribute uniformly into the Sn layer, avoiding the Kirkendall voids by providing the Cu atoms locally instead of all from the Cu/Sn interfaces for Cu-Sn reactions. The IMC resistance is also reduced as the 200-nm Sn layer forms an ultrathin IMC layer. A large-scale bump array has been bonded successfully, and a single bond resistance of 6.5 m<inline-formula> <tex-math>$\\\\Omega $ </tex-math></inline-formula> and a specific contact resistivity (SCR) of <inline-formula> <tex-math>$1.0\\\\times 10^{-}9 ~\\\\Omega \\\\cdot $ </tex-math></inline-formula> cm2 have been obtained.\",\"PeriodicalId\":13092,\"journal\":{\"name\":\"IEEE Transactions on Electron Devices\",\"volume\":\"72 3\",\"pages\":\"1276-1281\"},\"PeriodicalIF\":2.9000,\"publicationDate\":\"2025-02-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Electron Devices\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10870278/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Electron Devices","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10870278/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Low-Resistance Interconnects by Bonding Porous Cu Bumps and Ultrathin Cu/Sn Pads
CuSn-Cu bonding is widely used in 2.5-D integration due to the ease of operation. However, it suffers from high bond resistance due to the high resistivity of Cu-Sn intermetallic compounds (IMCs) and the high contact resistance due to the Kirkendall voids at the Cu/IMC interfaces. We report a low-resistance CuSn-Cu interconnect fabricated by bonding a porous Cu bump and a Cu-Sn pad with a 200-nm Sn layer. The porous Cu bump, fabricated by treating normal Cu-Sn bumps with oxygen and formic acid, is bonded with the Cu-Sn pad through solid-state bonding at 100 °C under a 5-MPa pressure, followed by 250 °C annealing. The bonding pressure presses the porous Cu to distribute uniformly into the Sn layer, avoiding the Kirkendall voids by providing the Cu atoms locally instead of all from the Cu/Sn interfaces for Cu-Sn reactions. The IMC resistance is also reduced as the 200-nm Sn layer forms an ultrathin IMC layer. A large-scale bump array has been bonded successfully, and a single bond resistance of 6.5 m$\Omega $ and a specific contact resistivity (SCR) of $1.0\times 10^{-}9 ~\Omega \cdot $ cm2 have been obtained.
期刊介绍:
IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.