紧凑型单级输入输出轨对轨AB级缓冲放大器,具有非对称输出结构

IF 2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Solid-State Circuits Letters Pub Date : 2025-03-18 DOI:10.1109/LSSC.2025.3551357
Young-Ju Oh;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong
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引用次数: 0

摘要

这封信介绍了一个紧凑的单级缓冲放大器,设计用于驱动大范围的容性负载(CL)。与以前的单级轨对轨放大器相比,为了进一步降低功耗和硅面积,本信函提出了不对称轨对轨级AB输出结构。为了实现高摆率,该放大器采用了正反馈回路和动态浮动节点。原型芯片成功地驱动了宽范围的CL,从250 pF到15 nF,同时实现了快速的瞬态响应。该芯片采用0.18- $\mu $ m CMOS工艺制备。
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Compact Single-Stage Input and Output Rail-to-Rail Class AB Buffer Amplifier With an Asymmetric Output Structure
This letter presents a compact single-stage buffer amplifier designed to drive a wide range of capacitive loads (CL). To further reduce power consumption and silicon area compared to previous single-stage rail-to-rail amplifiers, this letter proposes an asymmetric rail-to-rail class AB output structure. To achieve a high slew rate, the proposed amplifier employs positive feedback loops and a dynamic floating node. A prototype chip successfully drove a wide range of CL, from 250 pF to 15 nF, while achieving a fast transient response. The chip was fabricated using a 0.18- $\mu $ m CMOS process.
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来源期刊
IEEE Solid-State Circuits Letters
IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering
CiteScore
4.30
自引率
3.70%
发文量
52
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