Tahsin Ahmed Mozaffor Onik , Chia Ching Kee , Yung Cheng Wong , Ahmad Hafiz Jafarul Tarek , Prastika Krisma Jiwanti , Yew Hoong Wong
{"title":"优化热氧化温度以提高Ge半导体衬底上Ho2O3超薄膜栅介电材料的结构和电学性能","authors":"Tahsin Ahmed Mozaffor Onik , Chia Ching Kee , Yung Cheng Wong , Ahmad Hafiz Jafarul Tarek , Prastika Krisma Jiwanti , Yew Hoong Wong","doi":"10.1016/j.apsusc.2025.163224","DOIUrl":null,"url":null,"abstract":"<div><div>This study systematically characterized the structural, morphological and electrical properties of sputtered Ho/Ge interface after subsequent thermal oxidation in O<sub>2</sub> ambient varying deposition temperature from 450 °C–550 °C for metal oxide semiconductor capacitor (MOSCAP) device. The XRD analysis confirmed presence of cubic c-Ho<sub>2</sub>O<sub>3</sub> and tetragonal and cubic GeO<sub>2</sub> while the effect of crystallite size and micro-strain on electrical performance has been reported. As observed in XPS, 500 °C thermal oxidation condition has been conducive for exhibiting more stoichiometric phase of Ho<sub>2</sub>O<sub>3</sub>. This condition helped to limit irregular O diffusion toward substrate facilitating more controlled Ge activation and minimized uneven intermixing. Thereby, inhibited unstable interfacial (IL) layer sub-oxides, GeO<sub>x</sub> resulting more stable and compact interface Ho<sub>2</sub>O<sub>3</sub>/ IL (GeO<sub>2</sub> + GeO<sub>x</sub>). However, thermal budget of 550 °C led thicker interfacial layer due to over-oxidation corresponding severely defected Ho<sub>2</sub>O<sub>3</sub>/(GeO<sub>2</sub> + GeO<sub>x</sub>) interface degrading device operation. HRTEM further confirmed double stacked amorphous Ho<sub>2</sub>O<sub>3</sub>/IL structure ranging physical thickness from 7.04–10 nm. The reduction of structural defect at optimum oxidation condition 500 °C imposed a conduction band offset of 1.77 eV which impeded uneven electron transportation from Ge CB edge into the interface of Ho<sub>2</sub>O<sub>3</sub>/IL leading enhanced electrical breakdown at <span><math><mrow><msub><mi>J</mi><mi>g</mi></msub><mspace></mspace></mrow></math></span> 10<sup>-6</sup> Acm<sup>−2</sup> withstanding electrical breakdown field, <span><math><mrow><msub><mi>E</mi><mrow><mi>BD</mi></mrow></msub><mspace></mspace></mrow></math></span> 7.93 MVcm<sup>−1</sup>. Therefore, controlling the temperature set up for oxidized Ho/Ge could offer thinner GeO<sub>x</sub> layer improving the <span><math><mi>k</mi></math></span> 12.54 corresponding EOT 2.65 nm while reducing <span><math><msub><mi>Q</mi><mrow><mi>eff</mi></mrow></msub></math></span> and <span><math><msub><mi>Q</mi><mrow><mi>it</mi></mrow></msub></math></span> and <span><math><msub><mi>D</mi><mrow><mi>it</mi></mrow></msub></math></span> 10<sup>12</sup> eV<sup>−1</sup> cm<sup>−2</sup>. In outline, Ho<sub>2</sub>O<sub>3</sub> is projected to be a potential candidate as dielectric insulator for Ge-based MOSCAP devices.</div></div>","PeriodicalId":247,"journal":{"name":"Applied Surface Science","volume":"701 ","pages":"Article 163224"},"PeriodicalIF":6.9000,"publicationDate":"2025-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Optimizing thermal oxidation temperature for enhanced structural and electrical properties of Ho2O3 ultrathin-film gate dielectric on Ge semiconductor substrate\",\"authors\":\"Tahsin Ahmed Mozaffor Onik , Chia Ching Kee , Yung Cheng Wong , Ahmad Hafiz Jafarul Tarek , Prastika Krisma Jiwanti , Yew Hoong Wong\",\"doi\":\"10.1016/j.apsusc.2025.163224\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>This study systematically characterized the structural, morphological and electrical properties of sputtered Ho/Ge interface after subsequent thermal oxidation in O<sub>2</sub> ambient varying deposition temperature from 450 °C–550 °C for metal oxide semiconductor capacitor (MOSCAP) device. The XRD analysis confirmed presence of cubic c-Ho<sub>2</sub>O<sub>3</sub> and tetragonal and cubic GeO<sub>2</sub> while the effect of crystallite size and micro-strain on electrical performance has been reported. As observed in XPS, 500 °C thermal oxidation condition has been conducive for exhibiting more stoichiometric phase of Ho<sub>2</sub>O<sub>3</sub>. This condition helped to limit irregular O diffusion toward substrate facilitating more controlled Ge activation and minimized uneven intermixing. Thereby, inhibited unstable interfacial (IL) layer sub-oxides, GeO<sub>x</sub> resulting more stable and compact interface Ho<sub>2</sub>O<sub>3</sub>/ IL (GeO<sub>2</sub> + GeO<sub>x</sub>). However, thermal budget of 550 °C led thicker interfacial layer due to over-oxidation corresponding severely defected Ho<sub>2</sub>O<sub>3</sub>/(GeO<sub>2</sub> + GeO<sub>x</sub>) interface degrading device operation. HRTEM further confirmed double stacked amorphous Ho<sub>2</sub>O<sub>3</sub>/IL structure ranging physical thickness from 7.04–10 nm. The reduction of structural defect at optimum oxidation condition 500 °C imposed a conduction band offset of 1.77 eV which impeded uneven electron transportation from Ge CB edge into the interface of Ho<sub>2</sub>O<sub>3</sub>/IL leading enhanced electrical breakdown at <span><math><mrow><msub><mi>J</mi><mi>g</mi></msub><mspace></mspace></mrow></math></span> 10<sup>-6</sup> Acm<sup>−2</sup> withstanding electrical breakdown field, <span><math><mrow><msub><mi>E</mi><mrow><mi>BD</mi></mrow></msub><mspace></mspace></mrow></math></span> 7.93 MVcm<sup>−1</sup>. Therefore, controlling the temperature set up for oxidized Ho/Ge could offer thinner GeO<sub>x</sub> layer improving the <span><math><mi>k</mi></math></span> 12.54 corresponding EOT 2.65 nm while reducing <span><math><msub><mi>Q</mi><mrow><mi>eff</mi></mrow></msub></math></span> and <span><math><msub><mi>Q</mi><mrow><mi>it</mi></mrow></msub></math></span> and <span><math><msub><mi>D</mi><mrow><mi>it</mi></mrow></msub></math></span> 10<sup>12</sup> eV<sup>−1</sup> cm<sup>−2</sup>. In outline, Ho<sub>2</sub>O<sub>3</sub> is projected to be a potential candidate as dielectric insulator for Ge-based MOSCAP devices.</div></div>\",\"PeriodicalId\":247,\"journal\":{\"name\":\"Applied Surface Science\",\"volume\":\"701 \",\"pages\":\"Article 163224\"},\"PeriodicalIF\":6.9000,\"publicationDate\":\"2025-08-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Applied Surface Science\",\"FirstCategoryId\":\"88\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0169433225009389\",\"RegionNum\":2,\"RegionCategory\":\"材料科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"2025/4/19 0:00:00\",\"PubModel\":\"Epub\",\"JCR\":\"Q2\",\"JCRName\":\"CHEMISTRY, PHYSICAL\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Applied Surface Science","FirstCategoryId":"88","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0169433225009389","RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2025/4/19 0:00:00","PubModel":"Epub","JCR":"Q2","JCRName":"CHEMISTRY, PHYSICAL","Score":null,"Total":0}
引用次数: 0
摘要
本研究系统地表征了金属氧化物半导体电容器(MOSCAP)器件在450 °C - 550 °C O2环境下热氧化后溅射Ho/Ge界面的结构、形态和电学性能。XRD分析证实了立方c-Ho2O3、四方和立方GeO2的存在,并报道了晶粒尺寸和微应变对电性能的影响。在XPS中观察到,500 ℃的热氧化条件有利于Ho2O3的化学计量相的形成。这种条件有助于限制不规则的O向衬底扩散,促进更可控的Ge活化和最小化不均匀混合。从而抑制了不稳定界面(IL)层的亚氧化物,得到了更稳定致密的界面Ho2O3/ IL (GeO2 + GeOx)。然而,550 °C的热收支导致过氧化导致界面层变厚,相应地严重缺陷Ho2O3/(GeO2 + GeOx)界面降解器件运行。HRTEM进一步证实了物理厚度为7.04-10 nm的Ho2O3/IL双堆叠非晶结构。在500 °C的最佳氧化条件下,结构缺陷的减少导致了1.77 eV的导带偏移,这阻碍了电子从Ge CB边缘到Ho2O3/IL界面的不均匀传输,导致在jgjg10 -6 Acm−2,EBDEBD 7.93 MVcm−1的电击穿增强。因此,控制氧化Ho/Ge的温度设置可以提供更薄的GeOx层,提高kk 12.54对应的EOT 2.65 nm,同时降低QeffQeff和QitQit和DitDit 1012 eV−1 cm−2。总体而言,Ho2O3有望成为ge基MOSCAP器件的介电绝缘体。
Optimizing thermal oxidation temperature for enhanced structural and electrical properties of Ho2O3 ultrathin-film gate dielectric on Ge semiconductor substrate
This study systematically characterized the structural, morphological and electrical properties of sputtered Ho/Ge interface after subsequent thermal oxidation in O2 ambient varying deposition temperature from 450 °C–550 °C for metal oxide semiconductor capacitor (MOSCAP) device. The XRD analysis confirmed presence of cubic c-Ho2O3 and tetragonal and cubic GeO2 while the effect of crystallite size and micro-strain on electrical performance has been reported. As observed in XPS, 500 °C thermal oxidation condition has been conducive for exhibiting more stoichiometric phase of Ho2O3. This condition helped to limit irregular O diffusion toward substrate facilitating more controlled Ge activation and minimized uneven intermixing. Thereby, inhibited unstable interfacial (IL) layer sub-oxides, GeOx resulting more stable and compact interface Ho2O3/ IL (GeO2 + GeOx). However, thermal budget of 550 °C led thicker interfacial layer due to over-oxidation corresponding severely defected Ho2O3/(GeO2 + GeOx) interface degrading device operation. HRTEM further confirmed double stacked amorphous Ho2O3/IL structure ranging physical thickness from 7.04–10 nm. The reduction of structural defect at optimum oxidation condition 500 °C imposed a conduction band offset of 1.77 eV which impeded uneven electron transportation from Ge CB edge into the interface of Ho2O3/IL leading enhanced electrical breakdown at 10-6 Acm−2 withstanding electrical breakdown field, 7.93 MVcm−1. Therefore, controlling the temperature set up for oxidized Ho/Ge could offer thinner GeOx layer improving the 12.54 corresponding EOT 2.65 nm while reducing and and 1012 eV−1 cm−2. In outline, Ho2O3 is projected to be a potential candidate as dielectric insulator for Ge-based MOSCAP devices.
期刊介绍:
Applied Surface Science covers topics contributing to a better understanding of surfaces, interfaces, nanostructures and their applications. The journal is concerned with scientific research on the atomic and molecular level of material properties determined with specific surface analytical techniques and/or computational methods, as well as the processing of such structures.