Low-Power Approximate RPR Scheme for Unsigned Integer Arithmetic Computation

A scheme often used for error tolerance of arithmetic circuits is the so-called Reduced Precision Redundancy (RPR). Rather than replicating multiple times the entire module, RPR uses reduced precision (inexact) copies to significantly reduce the redundancy overhead, while still being able to correct the largest errors. This paper focuses on the low-power operation for RPR; a new scheme is proposed. At circuit level, power gating is initially utilized in the arithmetic modules to power off one of the modules (i.e., the exact module) when the inexact modules’ error is smaller than the threshold. The proposed design is applicable to (unsigned integer) addition, multiplication, and MAC (multiply and add) by proposing RPR implementations that reduce the power consumption with a limited impact on its error correction capability. The proposed schemes have been implemented and tested for various applications (image and DCT processing). The results show that they can significantly reduce power consumption; moreover, the simulation results show that the Mean Square Error (MSE) at the proposed schemes’ output is low.