Pub Date : 2025-11-07DOI: 10.1109/OJNANO.2025.3630545
Ioannis K. Chatzipaschalis;Pantelis Fraidakis;Georgios K. Kleitsiotis;Ioannis Tompris;Athanasios Passias;Emmanouil Stavroulakis;Evangelos Tsipas;Theodoros Panagiotis Chatzinikolaou;Karolos-Alexandros Tsakalos;Konstantinos Rallis;Iosif-Angelos Fyrigos;Vasileios Ntinas;Antonio Rubio;Georgios Ch. Sirakoulis
Memristors and crossbar arrays are increasingly regarded as fundamental nanotechnology components for future computing and storage technologies, with promising applications in neuromorphic systems, non-volatile memories, and in-memory processing. However, their characterization and programming require precise waveform generation and reproducible signal control, which pose non-trivial challenges in experimental workflows. Developing dedicated software for waveform design in this context is particularly demanding, as it must support diverse signal types, customizable timing, and the coordination of row/column activations in crossbar architectures, while remaining intuitive for non-specialist users. This paper presents WaCPro, an open-source application that integrates waveform generation, crossbar mapping, visualization, and export functionalities into a single platform for the characterization and programming of nanoscale memristive devices and crossbar arrays. Implemented in MATLAB with a modular architecture and a graphical user interface, WaCPro enables the design and export of precisely-timed waveforms essential for the electrical stimulation of nanodevices. Export functions produce simulation- and instrumentation-ready files in widely used formats, facilitating integration into laboratory workflows, highlighting the tool’s ability to bridge theory and experiment. Validation experiments demonstrate excellent waveform replication accuracy in both amplitude and timing, confirming the reliability of the proposed tool for nanoscale testing environments.
{"title":"WaCPro: An Open-Source Application for Waveform and Crossbar Programming in Nanotechnology Research","authors":"Ioannis K. Chatzipaschalis;Pantelis Fraidakis;Georgios K. Kleitsiotis;Ioannis Tompris;Athanasios Passias;Emmanouil Stavroulakis;Evangelos Tsipas;Theodoros Panagiotis Chatzinikolaou;Karolos-Alexandros Tsakalos;Konstantinos Rallis;Iosif-Angelos Fyrigos;Vasileios Ntinas;Antonio Rubio;Georgios Ch. Sirakoulis","doi":"10.1109/OJNANO.2025.3630545","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3630545","url":null,"abstract":"Memristors and crossbar arrays are increasingly regarded as fundamental nanotechnology components for future computing and storage technologies, with promising applications in neuromorphic systems, non-volatile memories, and in-memory processing. However, their characterization and programming require precise waveform generation and reproducible signal control, which pose non-trivial challenges in experimental workflows. Developing dedicated software for waveform design in this context is particularly demanding, as it must support diverse signal types, customizable timing, and the coordination of row/column activations in crossbar architectures, while remaining intuitive for non-specialist users. This paper presents WaCPro, an open-source application that integrates waveform generation, crossbar mapping, visualization, and export functionalities into a single platform for the characterization and programming of nanoscale memristive devices and crossbar arrays. Implemented in MATLAB with a modular architecture and a graphical user interface, WaCPro enables the design and export of precisely-timed waveforms essential for the electrical stimulation of nanodevices. Export functions produce simulation- and instrumentation-ready files in widely used formats, facilitating integration into laboratory workflows, highlighting the tool’s ability to bridge theory and experiment. Validation experiments demonstrate excellent waveform replication accuracy in both amplitude and timing, confirming the reliability of the proposed tool for nanoscale testing environments.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"170-178"},"PeriodicalIF":1.9,"publicationDate":"2025-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11231390","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145612137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-31DOI: 10.1109/OJNANO.2025.3628180
Andrea Meo;Giuseppe Borzì;Anna Giordano;Mario Carpentieri;Riccardo Tomasello;Giovanni Finocchio
Antiferromagnets (AFMs), having no stray fields and terahertz frequency dynamics, are ideal candidates to be employed as material elements in antennas in 5G/6G systems, where compact, efficient antennas working in the radiofrequency are essential. Voltage controlled magnetic anisotropy (VCMA) can provide an energy-efficient electrical method for controlling AFMs thanks to reduced ohmic losses. In addition, VCMA can drive parametric excitation achieving large-amplitude precession of the AFM state achieving greater efficiency than conventional excitation methods. Here, we theoretically study the response of the AFM induced by an incident radiofrequency electromagnetic (EM) wave, modelled as a time-dependent spatially inhomogeneous VCMA drive. We find that it is possible to excite parametrically the AFM at twice the input frequency, with total suppression of the input mode when the incident EM radiation satisfies the standing wave conditions. This shows how this system can be exploited as a receiving antenna in the radiofrequency range with the capability of generating an output signal with twice the input frequency. Therefore, AFM-based antennas could overcome current limitations in traditional antenna designs, offering an in-materio and low-power tool for terahertz communication applications.
{"title":"Antiferromagnetic Antenna Based on Parametric Resonance Driven by Spatially Non-Uniform Voltage-Controlled Magnetic Anisotropy","authors":"Andrea Meo;Giuseppe Borzì;Anna Giordano;Mario Carpentieri;Riccardo Tomasello;Giovanni Finocchio","doi":"10.1109/OJNANO.2025.3628180","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3628180","url":null,"abstract":"Antiferromagnets (AFMs), having no stray fields and terahertz frequency dynamics, are ideal candidates to be employed as material elements in antennas in 5G/6G systems, where compact, efficient antennas working in the radiofrequency are essential. Voltage controlled magnetic anisotropy (VCMA) can provide an energy-efficient electrical method for controlling AFMs thanks to reduced ohmic losses. In addition, VCMA can drive parametric excitation achieving large-amplitude precession of the AFM state achieving greater efficiency than conventional excitation methods. Here, we theoretically study the response of the AFM induced by an incident radiofrequency electromagnetic (EM) wave, modelled as a time-dependent spatially inhomogeneous VCMA drive. We find that it is possible to excite parametrically the AFM at twice the input frequency, with total suppression of the input mode when the incident EM radiation satisfies the standing wave conditions. This shows how this system can be exploited as a receiving antenna in the radiofrequency range with the capability of generating an output signal with twice the input frequency. Therefore, AFM-based antennas could overcome current limitations in traditional antenna designs, offering an in-materio and low-power tool for terahertz communication applications.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"146-152"},"PeriodicalIF":1.9,"publicationDate":"2025-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11223752","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-31DOI: 10.1109/OJNANO.2025.3627500
Anant Aravind Kulkarni;Shivam Verma
This article presents the generation of Greenberger–Horne–Zeilinger (GHZ) states using a spin-torque-based qubit architecture, introducing a hardware-native decomposition of the Hadamard and controlled NOT (CNOT) gates. Unlike optical or superconducting implementations, the proposed approach exploits intrinsic spin-transfer-torque dynamics to realize single-qubit and entangling operations with minimal external control. The method reduces gate overhead and decoherence, enabling high-fidelity (> 99%) GHZ formation. An unequal entanglement amplitude naturally arises from spin-torque non-linearities and is analytically characterized as a tunable property advantageous for quantum secret sharing (QSS) and asymmetric quantum communication schemes. Numerical simulations of state evolution and density-matrix fidelity validate the robustness and efficiency of the approach. The results demonstrate that current-driven spin-torque interactions provide a compact, energy-efficient platform for scalable multi-qubit entanglement, linking spintronic device physics with quantum information processing.
{"title":"Inequal Three Qubit Entanglement Using GHZ State Generation for Spin-Torque Based Qubit Architecture","authors":"Anant Aravind Kulkarni;Shivam Verma","doi":"10.1109/OJNANO.2025.3627500","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3627500","url":null,"abstract":"This article presents the generation of Greenberger–Horne–Zeilinger (GHZ) states using a spin-torque-based qubit architecture, introducing a hardware-native decomposition of the Hadamard and controlled NOT (CNOT) gates. Unlike optical or superconducting implementations, the proposed approach exploits intrinsic spin-transfer-torque dynamics to realize single-qubit and entangling operations with minimal external control. The method reduces gate overhead and decoherence, enabling high-fidelity (> 99%) GHZ formation. An unequal entanglement amplitude naturally arises from spin-torque non-linearities and is analytically characterized as a tunable property advantageous for quantum secret sharing (QSS) and asymmetric quantum communication schemes. Numerical simulations of state evolution and density-matrix fidelity validate the robustness and efficiency of the approach. The results demonstrate that current-driven spin-torque interactions provide a compact, energy-efficient platform for scalable multi-qubit entanglement, linking spintronic device physics with quantum information processing.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"179-186"},"PeriodicalIF":1.9,"publicationDate":"2025-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11223042","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145729403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High standby power has become a critical challenge for CMOS circuits below the 90 nm technology node as leakage currents continue to rise. Deeply scaled technologies not only increase power consumption due to subthreshold leakage but also make circuits more vulnerable to side-channel attacks (SCAs), especially leakage power analysis (LPA). Spin-based devices, like magnetic tunnel junctions (MTJs), offer key advantages such as non-volatility, high endurance, low standby power, and compatibility with CMOS technology. While switching mechanisms like spin torque transfer (STT) and spin-orbit torque (SOT) reduce energy consumption, their nanosecond-scale operation is constrained by spin precession. In contrast, all-optical switching (AOS) of MTJs enables magnetization reversal in sub-picosecond timescales, offering faster operation. This paper presents an optically switched fully non-volatile magnetic full-adder (OS-NV-MFA) circuit that uses AOS for input storage in MTJs, achieving both energy-efficiency and SCA-resilience. Results show that the OS-NV-MFA provides 56.11%, 50.78%, and 58.09% improvements in read latency and reduces total power by 76.69%, 53.28%, and 81.97% compared to NV-MFA, STT MFA, and SHE NV-MFA, respectively. Furthermore, the use of configurable and reference MTJs ensures indistinguishable subthreshold leakage currents for ‘0’ and ‘1’ states, enhancing resistance to LPA-based SCAs.
{"title":"Energy Efficient Ultra-Fast Optically Switched Fully Non-Volatile Magnetic Full Adder for Enhanced Side-Channel Attack Resilience","authors":"Surya Narain Dikshit;Alok Kumar Shukla;Sandeep Soni;Himanshu Fulara;Brajesh Kumar Kaushik","doi":"10.1109/OJNANO.2025.3625815","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3625815","url":null,"abstract":"High standby power has become a critical challenge for CMOS circuits below the 90 nm technology node as leakage currents continue to rise. Deeply scaled technologies not only increase power consumption due to subthreshold leakage but also make circuits more vulnerable to side-channel attacks (SCAs), especially leakage power analysis (LPA). Spin-based devices, like magnetic tunnel junctions (MTJs), offer key advantages such as non-volatility, high endurance, low standby power, and compatibility with CMOS technology. While switching mechanisms like spin torque transfer (STT) and spin-orbit torque (SOT) reduce energy consumption, their nanosecond-scale operation is constrained by spin precession. In contrast, all-optical switching (AOS) of MTJs enables magnetization reversal in sub-picosecond timescales, offering faster operation. This paper presents an optically switched fully non-volatile magnetic full-adder (OS-NV-MFA) circuit that uses AOS for input storage in MTJs, achieving both energy-efficiency and SCA-resilience. Results show that the OS-NV-MFA provides 56.11%, 50.78%, and 58.09% improvements in read latency and reduces total power by 76.69%, 53.28%, and 81.97% compared to NV-MFA, STT MFA, and SHE NV-MFA, respectively. Furthermore, the use of configurable and reference MTJs ensures indistinguishable subthreshold leakage currents for ‘0’ and ‘1’ states, enhancing resistance to LPA-based SCAs.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"162-169"},"PeriodicalIF":1.9,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11218157","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Spintronic Physically Unclonable Functions (PUFs) show promise in enhancing electronic system security due to their inherent randomness, low energy consumption, fast response times, and temperature stability. This paper presents a novel PUF based on voltage-gated spin-orbit torque magnetic tunnel junctions (VGSOT-MTJs) that compares the resistance of MTJ cells utilizing intrinsic process variations to get an output response. Compared to arbiter PUFs, the proposed PUF provides a significantly larger effective challenge-response pair (CRP) space by supporting multiple independent configurations and is also reconfigurable. The Proposed VGSOT-MTJ based PUF implemented at 45 nm technology achieves a lower energy consumption of 63.67 fJ/bit and a throughput of 0.27 Gb/s at a supply voltage of 1 V. The proposed PUF achieves near-ideal uniqueness of 50.2% and a high reliability of 97.3%. Moreover, the proposed PUF demonstrates strong resistance to both machine learning (ML) and side-channel attacks. An ML attack using a multilayer perceptron (MLP) yielded a prediction accuracy of under 55.27%, indicating the PUF’s resilience. The correlation power analysis (CPA) confirmed the PUF’s robustness against side-channel attacks. The designed VGSOT-MTJ based PUF shows robust performance with higher energy efficiency and is highly suitable for resource constrained Internet of Things applications.
{"title":"Energy-Efficient and Attacks Resilient PUF Design Exploiting VGSOT-MTJ","authors":"Kunal Kranti Das;Aditya Japa;Deepika Gupta;Brajesh Kumar Kaushik","doi":"10.1109/OJNANO.2025.3625466","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3625466","url":null,"abstract":"Spintronic Physically Unclonable Functions (PUFs) show promise in enhancing electronic system security due to their inherent randomness, low energy consumption, fast response times, and temperature stability. This paper presents a novel PUF based on voltage-gated spin-orbit torque magnetic tunnel junctions (VGSOT-MTJs) that compares the resistance of MTJ cells utilizing intrinsic process variations to get an output response. Compared to arbiter PUFs, the proposed PUF provides a significantly larger effective challenge-response pair (CRP) space by supporting multiple independent configurations and is also reconfigurable. The Proposed VGSOT-MTJ based PUF implemented at 45 nm technology achieves a lower energy consumption of 63.67 fJ/bit and a throughput of 0.27 Gb/s at a supply voltage of 1 V. The proposed PUF achieves near-ideal uniqueness of 50.2% and a high reliability of 97.3%. Moreover, the proposed PUF demonstrates strong resistance to both machine learning (ML) and side-channel attacks. An ML attack using a multilayer perceptron (MLP) yielded a prediction accuracy of under 55.27%, indicating the PUF’s resilience. The correlation power analysis (CPA) confirmed the PUF’s robustness against side-channel attacks. The designed VGSOT-MTJ based PUF shows robust performance with higher energy efficiency and is highly suitable for resource constrained Internet of Things applications.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"153-161"},"PeriodicalIF":1.9,"publicationDate":"2025-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11216370","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-13DOI: 10.1109/OJNANO.2025.3620878
Christina Villeneuve-Faure;Laurent Boudou;Gilbert Teyssedre;Kremena Makasheva
The intense work on development of unconventional approaches for computing and signal processing involves efforts on design and engineering of materials with tunable dielectric properties and switchable electrical state as conduction state. This is the case of in-memory computing using emerging non-volatile memories which has successfully opened up new prospects for neuromorphic computing via the option of high volume data traffic between processor and memory units but faces materials-related challenges mostly attributed to the intrinsic and non-ideal device properties and expresses complexity in hardware implementation. In the effort to advance on the concept we describe here a way for controlled modulation at nanoscale of the dielectric response of plasma synthesized silver nanoparticles (AgNPs)-based nanocomposites and a method for mapping their dielectric permittivity via Electrostatic Force Microscopy. By embedding a 2D-network of AgNPs close to the surface of thin SiO2-layers, one can locally modulate the relative dielectric permittivity (ϵr) of the device in a large range. The presence of AgNPs in the dielectric layer leads to a nanostructuration of the relative dielectric permittivity, with lower ϵr-values above the AgNPs and higher ones in-between them, when compared to the ϵr-value of a homogeneous SiO2. A nanostructuration factor is introduced to account for this effect. The nanostructured dielectric response is related to modulation of the electric field inside these AgNPs-based nanocomposites. The results in this work generate important contributions towards the practical applicability of such AgNPs-based nanocomposites for neuromorphic computing, which is considered as an important step towards device engineering.
{"title":"Dielectric Permittivity Modulation at Nanoscale in Plasma Synthesized Silver Nanoparticles Based Nanocomposites for In-Memory Computing","authors":"Christina Villeneuve-Faure;Laurent Boudou;Gilbert Teyssedre;Kremena Makasheva","doi":"10.1109/OJNANO.2025.3620878","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3620878","url":null,"abstract":"The intense work on development of unconventional approaches for computing and signal processing involves efforts on design and engineering of materials with tunable dielectric properties and switchable electrical state as conduction state. This is the case of in-memory computing using emerging non-volatile memories which has successfully opened up new prospects for neuromorphic computing via the option of high volume data traffic between processor and memory units but faces materials-related challenges mostly attributed to the intrinsic and non-ideal device properties and expresses complexity in hardware implementation. In the effort to advance on the concept we describe here a way for controlled modulation at nanoscale of the dielectric response of plasma synthesized silver nanoparticles (AgNPs)-based nanocomposites and a method for mapping their dielectric permittivity via Electrostatic Force Microscopy. By embedding a 2D-network of AgNPs close to the surface of thin SiO<sub>2</sub>-layers, one can locally modulate the relative dielectric permittivity (ϵ<sub>r</sub>) of the device in a large range. The presence of AgNPs in the dielectric layer leads to a nanostructuration of the relative dielectric permittivity, with lower ϵ<sub>r</sub>-values above the AgNPs and higher ones in-between them, when compared to the ϵ<sub>r</sub>-value of a homogeneous SiO<sub>2</sub>. A nanostructuration factor is introduced to account for this effect. The nanostructured dielectric response is related to modulation of the electric field inside these AgNPs-based nanocomposites. The results in this work generate important contributions towards the practical applicability of such AgNPs-based nanocomposites for neuromorphic computing, which is considered as an important step towards device engineering.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"131-145"},"PeriodicalIF":1.9,"publicationDate":"2025-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11202627","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-06DOI: 10.1109/OJNANO.2025.3616955
Praween Kumar Srivastava;Atul Kumar;Ajay Kumar
This work presents an analysis of the performance of Gallium Nitride Truncated Fin FinFETs (GaN-TF-FinFET) and compares them with conventional (C) FinFET, TF-FinFET, and silicon-on-insulator (SOI) TF-FinFET in analog and RF applications by using advanced simulation techniques at the 7 nm technology node and a low supply voltage (V DS = 0.3 V). This work evaluates key analog and high-frequency performance metrics of the GaN-TF-FinFET. The results show a 60% increase in drain current, leading to improved transconductance and switching speed. Additionally, the subthreshold slope is reduced to 34 mV/decade, representing a 93.74% improvement compared to the C-FinFET. Furthermore, the GaN-TF-FinFET demonstrates the lowest DIBL and the highest electron mobility. Parameters such as stray capacitance, f T, f MAX, GFP, TFP, and GTFP are superior in GaN-TF-FinFET, highlighting its high-frequency performance. Our findings demonstrate significant improvements in device efficiency and signal integrity, positioning GaN-TF-FinFET as a promising device for next-generation high-frequency applications.
{"title":"Comprehensive Investigation of Truncated Fin GaN FinFET for Improved Analog/RF Performance","authors":"Praween Kumar Srivastava;Atul Kumar;Ajay Kumar","doi":"10.1109/OJNANO.2025.3616955","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3616955","url":null,"abstract":"This work presents an analysis of the performance of Gallium Nitride Truncated Fin FinFETs (GaN-TF-FinFET) and compares them with conventional (C) FinFET, TF-FinFET, and silicon-on-insulator (SOI) TF-FinFET in analog and RF applications by using advanced simulation techniques at the 7 nm technology node and a low supply voltage (<italic>V</i> <sub>DS</sub> = 0.3 V). This work evaluates key analog and high-frequency performance metrics of the GaN-TF-FinFET. The results show a 60% increase in drain current, leading to improved transconductance and switching speed. Additionally, the subthreshold slope is reduced to 34 mV/decade, representing a 93.74% improvement compared to the C-FinFET. Furthermore, the GaN-TF-FinFET demonstrates the lowest DIBL and the highest electron mobility. Parameters such as stray capacitance, <italic>f</i> <sub>T</sub>, <italic>f</i> <sub>MAX</sub>, GFP, TFP, and GTFP are superior in GaN-TF-FinFET, highlighting its high-frequency performance. Our findings demonstrate significant improvements in device efficiency and signal integrity, positioning GaN-TF-FinFET as a promising device for next-generation high-frequency applications.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"123-130"},"PeriodicalIF":1.9,"publicationDate":"2025-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11189053","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-23DOI: 10.1109/OJNANO.2025.3613007
Gouranga Mandal;Mourina Ghosh;Pulak Mondal
In the field of neuromorphic computing, there is a growing need for high-frequency memristor emulators, especially for pattern recognition, image classification, and edge detection. A high-frequency memristor-based neural network can enhance synaptic weight updates and accelerate learning. This article presents an innovative memristor emulator circuit using CMOS-based building blocks: the Voltage Differencing Inverting Buffered Amplifier (VDIBA) and the Current Differencing Buffered Amplifier (CDBA). Our design achieves a maximum operating frequency of 60 MHz with a power consumption of only 2.25 mW. The memristor emulator is resistorless, electronically tunable, and functions in both grounded and floating configurations, as well as in incremental and decremental modes. We provide an analysis of transient behavior and voltage-current (V-I) characteristics, along with assessments of robustness and adaptability under various conditions. This memristor emulator is tailored for Adaptive Neural Networks (ANN) to mimic biological behavior and for Memristive Integrated-and-Fire (MIF) neuron circuits to replicate biological neurons, all developed using 180 nm CMOS technology. The proposed design has also been verified using ICs CA3080, LT1193, and AD844.
{"title":"Analog Building Blocks: VDIBA and CDBA Based Energy-Efficient High-Speed Memristor Emulator for Neuromorphic Applications","authors":"Gouranga Mandal;Mourina Ghosh;Pulak Mondal","doi":"10.1109/OJNANO.2025.3613007","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3613007","url":null,"abstract":"In the field of neuromorphic computing, there is a growing need for high-frequency memristor emulators, especially for pattern recognition, image classification, and edge detection. A high-frequency memristor-based neural network can enhance synaptic weight updates and accelerate learning. This article presents an innovative memristor emulator circuit using CMOS-based building blocks: the Voltage Differencing Inverting Buffered Amplifier (VDIBA) and the Current Differencing Buffered Amplifier (CDBA). Our design achieves a maximum operating frequency of 60 MHz with a power consumption of only 2.25 mW. The memristor emulator is resistorless, electronically tunable, and functions in both grounded and floating configurations, as well as in incremental and decremental modes. We provide an analysis of transient behavior and voltage-current (V-I) characteristics, along with assessments of robustness and adaptability under various conditions. This memristor emulator is tailored for Adaptive Neural Networks (ANN) to mimic biological behavior and for Memristive Integrated-and-Fire (MIF) neuron circuits to replicate biological neurons, all developed using 180 nm CMOS technology. The proposed design has also been verified using ICs CA3080, LT1193, and AD844.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"112-122"},"PeriodicalIF":1.9,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11175600","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-18DOI: 10.1109/OJNANO.2025.3611532
Vakkalakula Bharath Sreenivasulu;N Neelima;D Sudha;Prasad M;Asisa Kumar Panigrahy;Aruru Sai Kumar
In the proposed work, we have investigated the potential of the nanosheet FET design and temperature analysis at advanced nodes. Our investigation shows that the variation of gate length (LG) from 30 nm down to 3 nm, accompanied by using different gate dielectric materials, like silicon dioxide (only SiO2(3 nm)) and hafnium dioxide (HfO2) i.e., (SiO2 (2 nm) + HfO2 (1 nm)). The analysis is done at Linear (Ohmic) region to observe variable resistor for amplifiers or analog applications and saturation region to analyze the voltage controlled current sources (VCCS) applications. To comprehensively evaluate the electrical performance of the devices at the nano regime, quantum models are invoked to get accurate metrics like sub-threshold swing (SS), drain induced barrier lowering (DIBL), ON current (ION), OFF current (IOFF), and ION/IOFF ratio. Interestingly, even at the ultra-scaled dimensions of 5 nm and 3 nm, our devices exhibited remarkable electrical properties, with IOFF reaching 1013 at 5 nm and 1011 at 3 nm, while ION maintained a level of ∼106 at both dimensions when HfO2 gate stack is employed as the gate dielectric material. Our findings indicate that the integration of high-k materials becomes imperative for achieving superior device performance, particularly at reduced LG values. Moreover, we explored the scaling flexibility of the transistors by investigating additional parameters such as transconductance (gm) and transconductance generation factor (TGF). The impact of scaling of nanosheet FET towards temperature is also analyzed. The analysis shows that ultra scaled nanosheet FET is capable of driving amplifiers and VCCS applications with HfO2 gate stack compared to SiO2.
{"title":"Gate Stack Analysis of Junctionless Multi-Bridge-Channel FETs for Sub-3 nm Chips","authors":"Vakkalakula Bharath Sreenivasulu;N Neelima;D Sudha;Prasad M;Asisa Kumar Panigrahy;Aruru Sai Kumar","doi":"10.1109/OJNANO.2025.3611532","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3611532","url":null,"abstract":"In the proposed work, we have investigated the potential of the nanosheet FET design and temperature analysis at advanced nodes. Our investigation shows that the variation of gate length (<italic>L</i><sub>G</sub>) from 30 nm down to 3 nm, accompanied by using different gate dielectric materials, like silicon dioxide (only SiO<sub>2</sub>(3 nm)) and hafnium dioxide (HfO<sub>2</sub>) i.e., (SiO<sub>2</sub> (2 nm) + HfO<sub>2</sub> (1 nm)). The analysis is done at Linear (Ohmic) region to observe variable resistor for amplifiers or analog applications and saturation region to analyze the voltage controlled current sources (VCCS) applications. To comprehensively evaluate the electrical performance of the devices at the nano regime, quantum models are invoked to get accurate metrics like sub-threshold swing (SS), drain induced barrier lowering (DIBL), ON current (<italic>I</i><sub>ON</sub>), OFF current (<italic>I</i><sub>OFF</sub>), and <italic>I</i><sub>ON</sub><italic>/I</i><sub>OFF</sub> ratio. Interestingly, even at the ultra-scaled dimensions of 5 nm and 3 nm, our devices exhibited remarkable electrical properties, with <italic>I</i><sub>OFF</sub> reaching 10<sup>13</sup> at 5 nm and 10<sup>11</sup> at 3 nm, while <italic>I</i><sub>ON</sub> maintained a level of ∼10<sup>6</sup> at both dimensions when HfO<sub>2</sub> gate stack is employed as the gate dielectric material. Our findings indicate that the integration of high-<italic>k</i> materials becomes imperative for achieving superior device performance, particularly at reduced <italic>L</i><sub>G</sub> values. Moreover, we explored the scaling flexibility of the transistors by investigating additional parameters such as transconductance (g<sub>m</sub>) and transconductance generation factor (TGF). The impact of scaling of nanosheet FET towards temperature is also analyzed. The analysis shows that ultra scaled nanosheet FET is capable of driving amplifiers and VCCS applications with HfO<sub>2</sub> gate stack compared to SiO<sub>2</sub>.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"102-111"},"PeriodicalIF":1.9,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11171618","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-12DOI: 10.1109/OJNANO.2025.3598219
Adelcio M. de Souza;Daniel R. Celino;Regiane Ragi;Murilo A. Romero
This paper describes device models for the current-voltage (I–V) and capacitance-voltage (C–V) characteristics of ballistic nanotransistors based on two-dimensional (2D) materials. The proposed methodology introduces a novel, fully analytical, and explicit approach grounded in fundamental physical principles. This approach enables seamless integration into circuit simulators and provides clear insight into device operation. In contrast to the drift-diffusion models commonly found in the literature, this approach accurately describes the ballistic transport regime observed in state-of-the-art 2D nanotransistors. The proposed model was validated against both experimental and ab initio numerical simulations from the literature for devices based on molybdenum disulfide (MoS2) and indium selenide (InSe). The results show excellent agreement with the reference datasets, confirming the model’s accuracy and its suitability for designing advanced nanoelectronic devices and circuits.
{"title":"Analytical Model for Ballistic 2D Nanotransistors","authors":"Adelcio M. de Souza;Daniel R. Celino;Regiane Ragi;Murilo A. Romero","doi":"10.1109/OJNANO.2025.3598219","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3598219","url":null,"abstract":"This paper describes device models for the current-voltage (I–V) and capacitance-voltage (C–V) characteristics of ballistic nanotransistors based on two-dimensional (2D) materials. The proposed methodology introduces a novel, fully analytical, and explicit approach grounded in fundamental physical principles. This approach enables seamless integration into circuit simulators and provides clear insight into device operation. In contrast to the drift-diffusion models commonly found in the literature, this approach accurately describes the ballistic transport regime observed in state-of-the-art 2D nanotransistors. The proposed model was validated against both experimental and <italic>ab initio</i> numerical simulations from the literature for devices based on molybdenum disulfide (MoS<sub>2</sub>) and indium selenide (InSe). The results show excellent agreement with the reference datasets, confirming the model’s accuracy and its suitability for designing advanced nanoelectronic devices and circuits.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"91-101"},"PeriodicalIF":1.9,"publicationDate":"2025-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11123147","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144926864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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