一种具有精细阶跃频率缩放的增强型轻载效率降压调节器。

Nijad Anabtawi, Rony Ferzli, Haidar M Harmanani
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引用次数: 1

摘要

本文提出了一种用于噪声敏感应用的开关DC-DC降压变换器,具有增强的轻负载效率。采用基于sigma-delta调制器(ΣΔ)的控制器实现了低噪声、无杂散的运行,而通过引入精细步进频率缩放(FSFS)实现了轻负载效率,FSFS可以根据负载情况连续调整变换器的开关频率。采用跳模(连续导通模式(CCM)/间断导通模式(DCM))和全数字化实现进一步提高了调节效率。此外,该变换器通过重新配置ΣΔ调制器的量化步长和在环路滤波器中引入抖动,在整个负载范围内保持低输出电压纹波。所提出的调制器在14nm块体CMOS工艺上实现,并通过布局后仿真验证。它在重负载条件下达到95%的峰值效率,在轻负载条件下达到79%,在轻负载下最大电压纹波为15mV。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

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An Enhanced Light-Load Efficiency Step Down Regulator with Fine Step Frequency Scaling.

This paper presents a switching DC-DC Buck converter with enhanced light-load efficiency for use in noise-sensitive applications. Low noise, spur free operation is achieved by using a sigma-delta-modulator (ΣΔ) based controller, while light load efficiency is realized through the introduction of fine step frequency scaling (FSFS) which continuously adjusts the switching frequency of the converter with load conditions. Regulation efficiency is further improved by adoption of mode hopping (continuous conduction mode (CCM)/discontinuous conduction mode (DCM)) and utilization of a fully digital implementation. Furthermore, the presented converter maintains low output voltage ripple across its entire load range by reconfiguring the ΣΔ modulator's quantization step and introducing dither to the loop filter. The proposed modulator was implemented in 14nm bulk CMOS process and validated with post layout simulations. It attains a peak efficiency of 95% at heavy load conditions and 79% at light loads with a maximum voltage ripple of 15mV at light loads.

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