Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O

This article discusses the method of using the functional protocol of an existing high-speed I/O port for testing. This method enables reduced GPIO pin requirement during manufacturing test and running full structural content while embedded in a functioning system. Frequency of on-chip scan networks can be increased as it is no longer limited by pin timing bottlenecks of regular, slow-speed I/Os. The same HSAT-based test infrastructure can be used for enabling system-level and in-system test for monitoring throughout the lifecycle of the chip.