M. Boumaour, S. Kermadi, S. Sali, Abdelkader El-Amrani, S. Mezghiche, L. Zougar, Sarah Boulahdjel, Y. Pellegrin
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Step by step, the implementation of the processes for the two wafer sizes (4” wafers and 6” half wafers) is compared and analyzed in terms of performance and throughput.\n\n\nFindings\nGlobally, the same process effectiveness is observed for both types of wafers with slightly better sheet resistance uniformity for the thermal diffusion carried out on the half wafers; however, the horizontal arrangement of the wafer carriers in the diffusion and the plasma-enhanced chemical vapor deposition tubes limits the thermal balance regarding the total number of cells processed per batch.\n\n\nOriginality/value\nIn terms of the development of prototypes on a preindustrial scale, this paves the way to further continue operating outdated equipment for high-performance processes (passivated emitter and rear contact, Tunnel oxide passivated contact (TOPCon)), while complying with current standards for silicon wafers up to M10 format.\n","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":" ","pages":""},"PeriodicalIF":0.7000,"publicationDate":"2021-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Adapting M2 silicon half-wafers processing on industrial-scale equipment dedicated to 4″ solar technology\",\"authors\":\"M. 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Adapting M2 silicon half-wafers processing on industrial-scale equipment dedicated to 4″ solar technology
Purpose
The purpose of this study is to address the issue of technology equipment formerly dedicated to the process of 4- and even 5-inch photovoltaic cells and whose use has become critical with the evolution of silicon wafer size standards (M2–M10). Fortunately, the recent concept of 6'' half-cut cell with its many advantages appears promising insofar as it offers the possibility of further extend the use of costly, still operational process equipment, but doomed to obsolescence.
Design/methodology/approach
In the background of a detailed Al-BSF process, the authors show how to experimentally adapt specific accessories and arrange 6” half-wafers to enable the upgrade of a complete industrial process of silicon solar cells at a lower cost. Step by step, the implementation of the processes for the two wafer sizes (4” wafers and 6” half wafers) is compared and analyzed in terms of performance and throughput.
Findings
Globally, the same process effectiveness is observed for both types of wafers with slightly better sheet resistance uniformity for the thermal diffusion carried out on the half wafers; however, the horizontal arrangement of the wafer carriers in the diffusion and the plasma-enhanced chemical vapor deposition tubes limits the thermal balance regarding the total number of cells processed per batch.
Originality/value
In terms of the development of prototypes on a preindustrial scale, this paves the way to further continue operating outdated equipment for high-performance processes (passivated emitter and rear contact, Tunnel oxide passivated contact (TOPCon)), while complying with current standards for silicon wafers up to M10 format.
期刊介绍:
Microelectronics International provides an authoritative, international and independent forum for the critical evaluation and dissemination of research and development, applications, processes and current practices relating to advanced packaging, micro-circuit engineering, interconnection, semiconductor technology and systems engineering. It represents a current, comprehensive and practical information tool. The Editor, Dr John Atkinson, welcomes contributions to the journal including technical papers, research papers, case studies and review papers for publication. Please view the Author Guidelines for further details.
Microelectronics International comprises a multi-disciplinary study of the key technologies and related issues associated with the design, manufacture, assembly and various applications of miniaturized electronic devices and advanced packages. Among the broad range of topics covered are:
• Advanced packaging
• Ceramics
• Chip attachment
• Chip on board (COB)
• Chip scale packaging
• Flexible substrates
• MEMS
• Micro-circuit technology
• Microelectronic materials
• Multichip modules (MCMs)
• Organic/polymer electronics
• Printed electronics
• Semiconductor technology
• Solid state sensors
• Thermal management
• Thick/thin film technology
• Wafer scale processing.