基于28nm技术节点的高密度、8T2R nvSRAM存储单元

IF 1.3 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Active and Passive Electronic Components Pub Date : 2023-02-14 DOI:10.1155/2023/2364341

Jiayu Yin, W.-J. Liao, Chengying Chen

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引用次数: 0

摘要

结合静态随机存取存储器(SRAM)和电阻式存储器(RRAM)，提出了一种改进的8T2R非易失性随机存取存储器(nvSRAM)存储单元。差速模式是在6T SRAM存储节点上增加一对1T1R RRAM。通过优化连接和布局方案，降低了功耗，提高了数据稳定性。nvSRAM存储单元采用UMC CMOS 28 nm 1p9m工艺实现。电源电压为0.9 V时，静态噪声/读写余量分别为0.35 V、0.16 V和0.41 V。数据存储/恢复时间分别为0.21 ns和0.18 ns，有效面积为0.97 μm2。

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A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node

Combining with a static random-access memory (SRAM) and resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell is proposed in this study. With differential mode, a pair of 1T1R RRAM is added to 6T SRAM storage node. By optimizing the connection and layout scheme, the power consumption is reduced and the data stability is improved. The nvSRAM memory cell is realized with UMC CMOS 28 nm 1p9m process. When the power supply voltage is 0.9 V, the static noise/read/write margin is 0.35 V, 0.16 V, and 0.41 V, respectively. The data storage/restoration time is 0.21 ns and 0.18 ns, respectively, with an active area of 0.97 μm2.

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来源期刊

Active and Passive Electronic Components ENGINEERING, ELECTRICAL & ELECTRONIC-

CiteScore

1.30

自引率

0.00%

发文量

审稿时长

13 weeks

期刊介绍： Active and Passive Electronic Components is an international journal devoted to the science and technology of all types of electronic components. The journal publishes experimental and theoretical papers on topics such as transistors, hybrid circuits, integrated circuits, MicroElectroMechanical Systems (MEMS), sensors, high frequency devices and circuits, power devices and circuits, non-volatile memory technologies such as ferroelectric and phase transition memories, and nano electronics devices and circuits.