Design and Implementation of a Reliable Reconfigurable Imaging System

Because of SRAM sensitivity to radiation, SRAM-based FPGA systems deployed in harsh environments require error mitigation methods to reduce their overall downtime. This paper presents a fault-tolerant reconfigurable imaging system that relies on the DPR feature for correcting errors in the configuration memory and loading camera system IPs. The system reliability is evaluated by injecting faults in the FPGA configuration memory at runtime using the Xilinx SEM IP. The faults are injected internally using the Internal Configuration Access Port (ICAP), which is shared between the fault injection core and system parts. The results showed that 95% of the errors can by corrected automatically. This paper also proposes a fast-Built-in-Self-Test (BIST) mitigation technique to reduce the overall downtime in case of errors. This technique can reduce the recovery time by 80%. Moreover, Triple Modular Redundancy (TMR) is used to increase the overall reliability without significantly increasing the resource overhead.