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引用次数: 0
摘要
近年来,通信行业发生了巨大的变化。由于通信设备的巨大发展,全球互联网连接网络广泛用于人类的所有活动。信息安全已成为所有依赖网络系统的用户和客户所关心的主要问题。密码学在应对这些挑战和提高网络中数据通信的保密性、完整性和身份验证方面发挥了重要作用。数据加密标准DES (Data Encryption Standard, DES)是现代网络系统中应用最为广泛的一种加密技术,几十年来一直被用于数字信息的加解密。DES被许多新的基于DES的加密方法所取代,如AES和3DES。与此同时,一些硬件工具也引起了研究人员和学者的广泛关注,他们对使用这些基于硬件的工具来设计和实现他们的模型建议很感兴趣。因此,本文采用VHDL语言设计了一个简化数据加密标准(S-DES)。本设计是在FPGA Altera板上进行综合、编译和实现的,该板由Quartus II软件环境和Altera Cyclone IV 4CX150FPGA器件组成。S-DES已成功地实现了少量的逻辑元件。
A FPGA Implementation of Simplified Data Encryption Standard Using VHDL
In recent years, dramatic changed has been made in communication sector. Due to enormous development in communication devices, globally internet-connected network largely used in all human activities. The security of information has been becoming a major concern for all users and clients, whom depend on network system. The cryptography has played significant role to combat these challenges and improve confidentiality, integrity, and authentication of data communication in the network. The Data Encryption Standard (DES) is one of most familiar type of cryptography and widely used in the modern network system, which has been adopted in encryption and decryption a digital information for several decades. The DES is replaced by a number of new cryptographical methods, which based on DES, like AES and 3DES. In the same time some hardware tools have gained a lot of attention and become interested for researchers and academics to design and implement their model proposals with these hardware-based tools. Therefore, this paper, shows the design of a Simplified Data Encryption Standard (S-DES) by using VHDL language. The design is synthesized, compiled and implemented on the FPGA Altera board, which, consists Quartus II software environment, and Altera Cyclone IV 4CX150FPGA device. The S-DES has been successfully implemented with few numbers of logic elements.