减小晶体管的短通道效应和减小模拟电路的尺寸

IF 1.3 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Active and Passive Electronic Components Pub Date : 2019-07-04 DOI:10.1155/2019/4578501

Zhaopeng Wei, G. Jacquemod, Y. Leduc, E. Foucauld, J. Prouvée, B. Blampey

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引用次数: 3

摘要

模拟集成电路从不遵循摩尔定律。这对无源元件尤其适用。由于短通道效应，我们必须实现更长的晶体管，特别是模拟单元。在本文中，我们提出了一种新的拓扑结构，利用FDSOI(完全耗尽绝缘体上硅)技术的一些优点，以减少模拟单元的尺寸。首先，选择一个电流反射镜来说明和验证一个新的设计。35nm晶体管长度的测量电流验证了我们新的交叉耦合后门拓扑结构。然后，还采用了基于互补逆变器的VCRO(压控环振荡器)来去除无源元件，减小了电路的尺寸。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits

Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.

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来源期刊

Active and Passive Electronic Components ENGINEERING, ELECTRICAL & ELECTRONIC-

CiteScore

1.30

自引率

0.00%

发文量

审稿时长

13 weeks

期刊介绍： Active and Passive Electronic Components is an international journal devoted to the science and technology of all types of electronic components. The journal publishes experimental and theoretical papers on topics such as transistors, hybrid circuits, integrated circuits, MicroElectroMechanical Systems (MEMS), sensors, high frequency devices and circuits, power devices and circuits, non-volatile memory technologies such as ferroelectric and phase transition memories, and nano electronics devices and circuits.