用于大尺寸内插器制造的双面硅过孔(DSSV)互连

IF 0.7 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC Microelectronics International Pub Date : 2023-01-20 DOI:10.1108/mi-07-2022-0139
Haibo Yang, Fengwei Dai, Liqiang Cao, Guofu Cao, Zhidan Fang, Qidong Wang
{"title":"用于大尺寸内插器制造的双面硅过孔(DSSV)互连","authors":"Haibo Yang, Fengwei Dai, Liqiang Cao, Guofu Cao, Zhidan Fang, Qidong Wang","doi":"10.1108/mi-07-2022-0139","DOIUrl":null,"url":null,"abstract":"\nPurpose\nA large-scale detection system with more data in short time bins, small dead space and small signal identification is the ideology the scientists pursuing. These proposed demands are able to be solved by 2.5 D integration. The substance of a 2.5 D integration is called silicon interposer, which consists of the through silicon via (TSV) and redistribution layer. However, the state-of-the-art silicon interposer is not able to sustain its own mechanical strength with the detector/readout array often sitting as standalone in large science facilities and fails to reduce the expansions on the installation of the components due to its insufficient thickness and size. This study aims to propose a moderation of current interposer with large-sized, standalone properties.\n\n\nDesign/methodology/approach\nThis paper proposes an interposer based on double-sided silicon vias (DSSVs) interconnection. Unlike conventional interposer that is interconnected by TSVs, DSSVs interposer is interconnected by top vias (T-vias) and bottom vias (B-vias).\n\n\nFindings\nThe fabrication process of DSSVs interposer is introduced, and the superiority of the double-sided interconnection process with two etch-stop layers is described in detail. The impact of different T-vias depth on DSSVs interconnections in the same wafer is discussed and two times PI opening processes are proposed to eliminate air bubbles in the B-via. The relationship between the interposer thickness and warpage is studied by finite element analysis simulation and experiment. The prototype of the DSSVs interposer with a size of 100  × 100 mm and a thickness of 318.2 µm is fabricated, and electrical tests including short tests and continuity tests are carried out.\n\n\nOriginality/value\nThis paper proposes a large-sized and stand-alone interposer based on DSSVs interconnection.\n","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":0.7000,"publicationDate":"2023-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Double-sided silicon vias (DSSVs) interconnection for large-sized interposer fabrication\",\"authors\":\"Haibo Yang, Fengwei Dai, Liqiang Cao, Guofu Cao, Zhidan Fang, Qidong Wang\",\"doi\":\"10.1108/mi-07-2022-0139\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"\\nPurpose\\nA large-scale detection system with more data in short time bins, small dead space and small signal identification is the ideology the scientists pursuing. These proposed demands are able to be solved by 2.5 D integration. The substance of a 2.5 D integration is called silicon interposer, which consists of the through silicon via (TSV) and redistribution layer. However, the state-of-the-art silicon interposer is not able to sustain its own mechanical strength with the detector/readout array often sitting as standalone in large science facilities and fails to reduce the expansions on the installation of the components due to its insufficient thickness and size. This study aims to propose a moderation of current interposer with large-sized, standalone properties.\\n\\n\\nDesign/methodology/approach\\nThis paper proposes an interposer based on double-sided silicon vias (DSSVs) interconnection. Unlike conventional interposer that is interconnected by TSVs, DSSVs interposer is interconnected by top vias (T-vias) and bottom vias (B-vias).\\n\\n\\nFindings\\nThe fabrication process of DSSVs interposer is introduced, and the superiority of the double-sided interconnection process with two etch-stop layers is described in detail. The impact of different T-vias depth on DSSVs interconnections in the same wafer is discussed and two times PI opening processes are proposed to eliminate air bubbles in the B-via. The relationship between the interposer thickness and warpage is studied by finite element analysis simulation and experiment. The prototype of the DSSVs interposer with a size of 100  × 100 mm and a thickness of 318.2 µm is fabricated, and electrical tests including short tests and continuity tests are carried out.\\n\\n\\nOriginality/value\\nThis paper proposes a large-sized and stand-alone interposer based on DSSVs interconnection.\\n\",\"PeriodicalId\":49817,\"journal\":{\"name\":\"Microelectronics International\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.7000,\"publicationDate\":\"2023-01-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics International\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://doi.org/10.1108/mi-07-2022-0139\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics International","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1108/mi-07-2022-0139","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

目的在短时间内实现数据量大、死区小、信号识别小的大规模检测系统是科学家们所追求的思想。这些要求可以通过2.5 D集成来解决。2.5 D集成的实质被称为硅中间层,它由硅通孔(TSV)和重分配层组成。然而,最先进的硅中间体无法维持其自身的机械强度,探测器/读出阵列通常作为独立的设备安装在大型科学设施中,并且由于其厚度和尺寸不足而无法减少组件安装的扩展。本研究旨在提出一种具有大尺寸,独立属性的当前中介器。设计/方法/方法本文提出了一种基于双面硅通孔(dssv)互连的介面器。与传统的由tsv连接的中介器不同,dssv中介器由顶部通孔(t -通孔)和底部通孔(b -通孔)连接。研究结果介绍了dssv间插板的制作工艺,并详细描述了双止蚀层双面互连工艺的优越性。讨论了不同的t孔深度对同一晶圆上dssv互连的影响,并提出了两次PI打开工艺以消除b孔中的气泡。采用有限元分析、仿真和实验相结合的方法研究了中间板厚度与翘曲量的关系。制作了尺寸为100 × 100 mm、厚度为318.2µm的dssv中间插板样机,并进行了包括短接试验和连续性试验在内的电学试验。本文提出了一种基于dssv互联的大型单机中介器。
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Double-sided silicon vias (DSSVs) interconnection for large-sized interposer fabrication
Purpose A large-scale detection system with more data in short time bins, small dead space and small signal identification is the ideology the scientists pursuing. These proposed demands are able to be solved by 2.5 D integration. The substance of a 2.5 D integration is called silicon interposer, which consists of the through silicon via (TSV) and redistribution layer. However, the state-of-the-art silicon interposer is not able to sustain its own mechanical strength with the detector/readout array often sitting as standalone in large science facilities and fails to reduce the expansions on the installation of the components due to its insufficient thickness and size. This study aims to propose a moderation of current interposer with large-sized, standalone properties. Design/methodology/approach This paper proposes an interposer based on double-sided silicon vias (DSSVs) interconnection. Unlike conventional interposer that is interconnected by TSVs, DSSVs interposer is interconnected by top vias (T-vias) and bottom vias (B-vias). Findings The fabrication process of DSSVs interposer is introduced, and the superiority of the double-sided interconnection process with two etch-stop layers is described in detail. The impact of different T-vias depth on DSSVs interconnections in the same wafer is discussed and two times PI opening processes are proposed to eliminate air bubbles in the B-via. The relationship between the interposer thickness and warpage is studied by finite element analysis simulation and experiment. The prototype of the DSSVs interposer with a size of 100  × 100 mm and a thickness of 318.2 µm is fabricated, and electrical tests including short tests and continuity tests are carried out. Originality/value This paper proposes a large-sized and stand-alone interposer based on DSSVs interconnection.
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来源期刊
Microelectronics International
Microelectronics International 工程技术-材料科学:综合
CiteScore
1.90
自引率
9.10%
发文量
28
审稿时长
>12 weeks
期刊介绍: Microelectronics International provides an authoritative, international and independent forum for the critical evaluation and dissemination of research and development, applications, processes and current practices relating to advanced packaging, micro-circuit engineering, interconnection, semiconductor technology and systems engineering. It represents a current, comprehensive and practical information tool. The Editor, Dr John Atkinson, welcomes contributions to the journal including technical papers, research papers, case studies and review papers for publication. Please view the Author Guidelines for further details. Microelectronics International comprises a multi-disciplinary study of the key technologies and related issues associated with the design, manufacture, assembly and various applications of miniaturized electronic devices and advanced packages. Among the broad range of topics covered are: • Advanced packaging • Ceramics • Chip attachment • Chip on board (COB) • Chip scale packaging • Flexible substrates • MEMS • Micro-circuit technology • Microelectronic materials • Multichip modules (MCMs) • Organic/polymer electronics • Printed electronics • Semiconductor technology • Solid state sensors • Thermal management • Thick/thin film technology • Wafer scale processing.
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