An Improved Unified AES Implementation using FPGA

Encryption is an essential process in electronic data transmission because it securely protects the data from unauthorized access. In this digital era, information and its security are of great concern with technology advancements. As we have entered into 5G technology that targets end-to-end security and speed to communicate with intelligent devices. These devices and systems need an AES module having both the operation as encryption and decryption in a single module to communicate in duplex mode to access the information in a real-time environment. This article has architecture of a unified module with modified round operation and has been implemented on Virtex-7 FPGA platform. Mix column adds vertical alteration in the algorithm and this design has managed the utilization of Mix column block to make an optimized AES algorithm. The unified AES has achieved a maximum frequency of 290.3MHz and resource utilization of 9416 slice LUTs design, including some modification in traditional AES, resulting in less resource utilization and high throughput.