{"title":"利用模糊技术实现DST的一种新的整数算法","authors":"D. Chiper","doi":"10.56958/jesi.2022.7.1.97","DOIUrl":null,"url":null,"abstract":"In this paper we propose a new VLSI algorithm for an integer based discrete sine transform (IntDST) that allows an efficient VLSI implementation using systolic arrays. The proposed algorithm have all the benefits of an integer transform as a good approximation of irrational transform coefficients and allows an efficient restructuring into a regular and modular computation structure that allows an efficient VLSI implementation using systolic arrays. An efficient VLSI architecture for discrete sine transform can be obtained that allows an efficient incorporation of the obfuscation technique that significantly improves the hardware security and offering high speed performances due to a concurrent computation and using pipelining technique at a low hardware complexity.","PeriodicalId":52936,"journal":{"name":"Journal of Engineering Sciences and Innovation","volume":" ","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2022-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A new integer algorithm for an efficient VLSI implementation of DST using obfuscation technique\",\"authors\":\"D. Chiper\",\"doi\":\"10.56958/jesi.2022.7.1.97\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we propose a new VLSI algorithm for an integer based discrete sine transform (IntDST) that allows an efficient VLSI implementation using systolic arrays. The proposed algorithm have all the benefits of an integer transform as a good approximation of irrational transform coefficients and allows an efficient restructuring into a regular and modular computation structure that allows an efficient VLSI implementation using systolic arrays. An efficient VLSI architecture for discrete sine transform can be obtained that allows an efficient incorporation of the obfuscation technique that significantly improves the hardware security and offering high speed performances due to a concurrent computation and using pipelining technique at a low hardware complexity.\",\"PeriodicalId\":52936,\"journal\":{\"name\":\"Journal of Engineering Sciences and Innovation\",\"volume\":\" \",\"pages\":\"\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-03-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Engineering Sciences and Innovation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.56958/jesi.2022.7.1.97\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Engineering Sciences and Innovation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.56958/jesi.2022.7.1.97","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new integer algorithm for an efficient VLSI implementation of DST using obfuscation technique
In this paper we propose a new VLSI algorithm for an integer based discrete sine transform (IntDST) that allows an efficient VLSI implementation using systolic arrays. The proposed algorithm have all the benefits of an integer transform as a good approximation of irrational transform coefficients and allows an efficient restructuring into a regular and modular computation structure that allows an efficient VLSI implementation using systolic arrays. An efficient VLSI architecture for discrete sine transform can be obtained that allows an efficient incorporation of the obfuscation technique that significantly improves the hardware security and offering high speed performances due to a concurrent computation and using pipelining technique at a low hardware complexity.