事件驱动神经形态系统的脉冲神经网络通信与同步技术研究进展

IF 2.3 Q2 COMPUTER SCIENCE, THEORY & METHODS Array Pub Date : 2023-10-05 DOI:10.1016/j.array.2023.100323
Mahyar Shahsavari , David Thomas , Marcel van Gerven , Andrew Brown , Wayne Luk
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引用次数: 0

摘要

神经形态事件驱动系统通过利用尖峰神经网络(SNN)来模拟大脑的计算机制。神经形态系统有两个主要应用领域:在神经科学中模拟神经信息处理和在工程应用中充当认知计算的加速器。神经形态系统的一个显著特征是其异步或事件驱动的性质,但即使是事件驱动的系统也需要对神经元群体进行一些同步的时间管理,以确保有足够的时间来正确传递尖峰信息。在这项研究中,我们评估了为异步事件驱动计算系统添加同步功能而提出的三种不同算法。我们在POETS(部分有序事件触发系统)上运行这些算法,POETS是一个定制的基于FPGA的硬件平台,作为一种神经形态架构。本研究展示了不同大小SNN的模拟速度。我们探索了事件驱动的神经形态系统设计的基本方面,这些方面有助于高效的计算和通信。这些方面包括不同程度的连接、路由方法、到硬件组件的映射技术以及发射率。这项工作使用3072个可重新配置的处理核心,每个处理核心有16个硬件线程,对多达800万个神经元进行了硬件映射和模拟,每个神经元与多达1000个其他神经元相连。使用最佳的同步和通信方法,我们的架构设计分别比Brian模拟器和一个48芯片SpiNNaker节点实现了20倍和16倍的加速。最后,我们在同步、路由和通信方法方面将我们的平台与现有的大型神经形态系统进行了简要比较,以指导未来事件驱动的神经形态系统的发展。
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Advancements in spiking neural network communication and synchronization techniques for event-driven neuromorphic systems

Neuromorphic event-driven systems emulate the computational mechanisms of the brain through the utilization of spiking neural networks (SNN). Neuromorphic systems serve two primary application domains: simulating neural information processing in neuroscience and acting as accelerators for cognitive computing in engineering applications. A distinguishing characteristic of neuromorphic systems is their asynchronous or event-driven nature, but even event-driven systems require some synchronous time management of the neuron populations to guarantee sufficient time for the proper delivery of spiking messages. In this study, we assess three distinct algorithms proposed for adding a synchronization capability to asynchronous event-driven compute systems. We run these algorithms on POETS (Partially Ordered Event-Triggered Systems), a custom-built FPGA-based hardware platform, as a neuromorphic architecture. This study presents the simulation speed of SNNs of various sizes. We explore essential aspects of event-driven neuromorphic system design that contribute to efficient computation and communication. These aspects include varying degrees of connectivity, routing methods, mapping techniques onto hardware components, and firing rates. The hardware mapping and simulation of up to eight million neurons, where each neuron is connected to up to one thousand other neurons, are presented in this work using 3072 reconfigurable processing cores, each of which has 16 hardware threads. Using the best synchronization and communication methods, our architecture design demonstrates 20-fold and 16-fold speedups over the Brian simulator and one 48-chip SpiNNaker node, respectively. We conclude with a brief comparison between our platform and existing large-scale neuromorphic systems in terms of synchronization, routing, and communication methods, to guide the development of future event-driven neuromorphic systems.

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来源期刊
Array
Array Computer Science-General Computer Science
CiteScore
4.40
自引率
0.00%
发文量
93
审稿时长
45 days
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