采用高增益- bw积差跨阻放大器的16纳米FinFET工艺无电感光接收机前端

IF 2.4 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE open journal of circuits and systems Pub Date : 2023-01-01 DOI:10.1109/OJCAS.2023.3236567
Milad Haghi Kashani;Hossein Shakiba;Ali Sheikholeslami
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引用次数: 0

摘要

本文介绍了一种可提供高增益增益积的全差分跨阻放大器(TIA)。在所提出的结构中,采用级联码交叉耦合结构使级联码器件的有效跨导率增加一倍,从而提高了TIA的BW。此外,差分架构使用RC高通滤波器以及需要更小电容和电阻的缓冲级来实现。此外,在TIA的输入端采用了一个单端负电容产生(NCG)电路来部分补偿输入寄生电容。采用16nm FinFET工艺设计和布局的TIA,与采用所提出的TIA设计的级联编码和传统TIA相比,分别表现出57%和79%的优势。通过布局后仿真和统计分析,验证了该结构的有效性。仿真结果表明,在数据速率为56 Gbps PAM4、误码率(BER)为1e6的情况下,光接收机的峰值透阻增益为58.5 dB $\Omega $, BW为14.8 GHz,输入参考噪声为33.6 pA/ $ $ surd $ Hz,开眼值为30 mV。整个电路消耗49 mW,占用0.0076 mm 2的有源面积。
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An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process
In this paper, a fully-differential transimpedance amplifier (TIA) providing a high gain-BW product (GBP) is introduced. In the proposed architecture, a cascode cross-coupled structure is employed to double the effective transconductance of the cascode devices, improving the BW of the TIA. Moreover, a differential architecture is implemented using an RC high-pass filter along with a buffer stage requiring smaller capacitance and resistance. Furthermore, a single-ended negative capacitance generation (NCG) circuit is employed at the input of the TIA to partially compensate for the input parasitic capacitances. A TIA including the proposed techniques, designed and laid out in a 16-nm FinFET process, demonstrates 57% and 79% better figure-of-merit compared to cascode and conventional TIAs designed along with the proposed TIA for a fair comparison, respectively. Post-layout simulations in companion with statistical analysis are employed to verify the effectiveness of the proposed architecture. From simulation results, the optical receiver achieves a peak transimpedance gain of 58.5 dB $\Omega $ , a BW of 14.8 GHz, an input-referred noise of 33.6 pA/ $\surd $ Hz, and an eye-opening of 30 mV at a data-rate of 56 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole circuit consumes 49 mW and occupies an active area of 0.0076 mm 2.
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