Pub Date : 2024-07-16DOI: 10.1109/OJCAS.2024.3427693
Miad Laghaei;Hossein Shakiba;Ali Sheikholeslami
Multicarrier modulation, while providing a theoretical pathway to data rates approaching the Shannon limit and being extensively utilized in wireless communication, has encountered limited application in high-speed wireline communication. This limitation is primarily due to substantial large amplitude peaks, which necessitates a reduction in the signal’s power levels to circumvent signal clipping. This, in turn, results in a low signal-to-noise ratio (SNR) which puts these modulations at a serious disadvantage compared to conventional modulation schemes. This work proposes a novel companding solution in the design of the Continuous Time Linear Equalizer (CTLE) alongside nonlinear blocks to reduce Peak to Average Power Ratio (PAPR), therefore improving the overall link performance. This paper presents a PAPR reduction technique and its implementation in the receiver, distinguishing it from previous studies that place the compander at the transmitter where it fails to work in the presence of an Inter-Symbol Interference (ISI) channel. A theoretical study as well as an implementation of this method is provided, and the merits and performance improvements are demonstrated.
{"title":"A Companding Technique to Reduce Peak-to-Average Ratio in Discrete Multitone Wireline Receivers","authors":"Miad Laghaei;Hossein Shakiba;Ali Sheikholeslami","doi":"10.1109/OJCAS.2024.3427693","DOIUrl":"10.1109/OJCAS.2024.3427693","url":null,"abstract":"Multicarrier modulation, while providing a theoretical pathway to data rates approaching the Shannon limit and being extensively utilized in wireless communication, has encountered limited application in high-speed wireline communication. This limitation is primarily due to substantial large amplitude peaks, which necessitates a reduction in the signal’s power levels to circumvent signal clipping. This, in turn, results in a low signal-to-noise ratio (SNR) which puts these modulations at a serious disadvantage compared to conventional modulation schemes. This work proposes a novel companding solution in the design of the Continuous Time Linear Equalizer (CTLE) alongside nonlinear blocks to reduce Peak to Average Power Ratio (PAPR), therefore improving the overall link performance. This paper presents a PAPR reduction technique and its implementation in the receiver, distinguishing it from previous studies that place the compander at the transmitter where it fails to work in the presence of an Inter-Symbol Interference (ISI) channel. A theoretical study as well as an implementation of this method is provided, and the merits and performance improvements are demonstrated.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10599803","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141719644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Multiple parameter environment monitoring via wireless Internet of Thing sensors is growing rapidly, thanks to low power techniques of the node. More importantly, the ever more complex and highly efficient energy harvesting systems enable long-term continuous monitoring in inaccessible environments without needing to change the battery. This paper reviews existing energy harvesting modalities, including photovoltaic, piezoelectric, pyroelectric, electromagnetic, and vibration, together with circuit techniques of interfacing power management circuits for energy harvesters. Moreover, techniques used to interface with multiple mode energy harvesters to obtain a stable output power with optimal power efficiency are discussed as an emerging direction. The state-of-the-art energy harvesting systems together with future development trends are provided.
{"title":"Low-Power On-Chip Energy Harvesting: From Interface Circuits Perspective","authors":"Shuang Song;Dehong Wang;Mengyu Li;Siyao Cao;Feijun Zheng;Kai Huang;Zhichao Tan;Sijun Du;Menglian Zhao","doi":"10.1109/OJCAS.2024.3423484","DOIUrl":"10.1109/OJCAS.2024.3423484","url":null,"abstract":"Multiple parameter environment monitoring via wireless Internet of Thing sensors is growing rapidly, thanks to low power techniques of the node. More importantly, the ever more complex and highly efficient energy harvesting systems enable long-term continuous monitoring in inaccessible environments without needing to change the battery. This paper reviews existing energy harvesting modalities, including photovoltaic, piezoelectric, pyroelectric, electromagnetic, and vibration, together with circuit techniques of interfacing power management circuits for energy harvesters. Moreover, techniques used to interface with multiple mode energy harvesters to obtain a stable output power with optimal power efficiency are discussed as an emerging direction. The state-of-the-art energy harvesting systems together with future development trends are provided.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2024-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10585308","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141551872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-18DOI: 10.1109/OJCAS.2024.3416397
Yu-Ping Huang;Yu-Sian Lu;Wei-Zen Chen
This paper presents the design of a 10 GHz dual-loop PLL with active cycle-jitter correction. In the main loop of the PLL, a sampling PD is utilized to suppress the in-band noise to reach the reference noise floor. On the other hand, to eliminate noise disturbance outside the PLL loop bandwidth, an active cycle-jitter correction (ACJC) loop is proposed and incorporated in this design. The ACJC utilizes a delay-discriminator based cycle jitter extractor and is performed at the subharmonic of VCO. It provides jitter suppression far beyond a conventional PLL loop bandwidth. An experimental prototype has been fabricated in a TSMC 40 nm CMOS process. By activating the ACJC, the spurious tones can be reduced by 12 dB when a 260MHz disturbance is injected without resort to sophisticated calibration. The integrated jitter from 1kHz to 260 MHz can be reduced from 413.7 fs to 293.21 fs, which corresponds to 29% improvement in jitter reduction. The PLL core consumes 22.1 mW. The chip area is about 0.97x0.96 mm2.
{"title":"A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction","authors":"Yu-Ping Huang;Yu-Sian Lu;Wei-Zen Chen","doi":"10.1109/OJCAS.2024.3416397","DOIUrl":"10.1109/OJCAS.2024.3416397","url":null,"abstract":"This paper presents the design of a 10 GHz dual-loop PLL with active cycle-jitter correction. In the main loop of the PLL, a sampling PD is utilized to suppress the in-band noise to reach the reference noise floor. On the other hand, to eliminate noise disturbance outside the PLL loop bandwidth, an active cycle-jitter correction (ACJC) loop is proposed and incorporated in this design. The ACJC utilizes a delay-discriminator based cycle jitter extractor and is performed at the subharmonic of VCO. It provides jitter suppression far beyond a conventional PLL loop bandwidth. An experimental prototype has been fabricated in a TSMC 40 nm CMOS process. By activating the ACJC, the spurious tones can be reduced by 12 dB when a 260MHz disturbance is injected without resort to sophisticated calibration. The integrated jitter from 1kHz to 260 MHz can be reduced from 413.7 fs to 293.21 fs, which corresponds to 29% improvement in jitter reduction. The PLL core consumes 22.1 mW. The chip area is about 0.97x0.96 mm2.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10561565","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141931942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-13DOI: 10.1109/OJCAS.2024.3414252
Jhoan Salinas;Hossein Shakiba;Ali Sheikholeslami
This paper describes an analog multi-tone receiver capable of processing three data streams running at 15 Gb/s, one in baseband and two in quadrature over carriers at 15GHz, achieving an aggregate rate of 45Gb/s over a single physical channel. The receiver maximizes bandwidth efficiency by using orthogonal sub-channels and avoids the need for analog to digital converters by incorporating a mixedsignal MIMO equalizer that can mitigate inter-symbol interference and inter-carrier interference. The system is designed and laid out in a 22nm FDSOI technology. Post-layout simulations are employed to verify the effectiveness of the proposed architecture, demonstrating a raw BER of 10−5 over a channel with an insertion loss of 14dB at 28GHz is achieved. The complete system has an energy efficiency of 6.6pJ/bit and occupies an active area of 0.29 mm2.
{"title":"A 45Gb/s Analog Multi-Tone Receiver Utilizing a 6-Tap MIMO-FFE in 22nm FDSOI","authors":"Jhoan Salinas;Hossein Shakiba;Ali Sheikholeslami","doi":"10.1109/OJCAS.2024.3414252","DOIUrl":"10.1109/OJCAS.2024.3414252","url":null,"abstract":"This paper describes an analog multi-tone receiver capable of processing three data streams running at 15 Gb/s, one in baseband and two in quadrature over carriers at 15GHz, achieving an aggregate rate of 45Gb/s over a single physical channel. The receiver maximizes bandwidth efficiency by using orthogonal sub-channels and avoids the need for analog to digital converters by incorporating a mixedsignal MIMO equalizer that can mitigate inter-symbol interference and inter-carrier interference. The system is designed and laid out in a 22nm FDSOI technology. Post-layout simulations are employed to verify the effectiveness of the proposed architecture, demonstrating a raw BER of 10−5 over a channel with an insertion loss of 14dB at 28GHz is achieved. The complete system has an energy efficiency of 6.6pJ/bit and occupies an active area of 0.29 mm2.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2024-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10556759","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141932010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-05DOI: 10.1109/OJCAS.2024.3409747
Bent Walther;Lukas Polzin;Marcel van Delden;Thomas Musch
Using physically separated multiple-input multiple-output (MIMO) systems for millimeter-wave measurement systems based on linear frequency chirps poses unique challenges for generating a modulated reference chirp to apply high coherence. The reference frequency chirp is crucial for the measurement accuracy of the overall system and should feature high bandwidth, low phase noise, and high linearity. For this reason, we present a novel architecture combining a fixed-integer phase-locked loop (PLL) with a fast-modulated frequency divider. Thus, modulated output frequencies of up to 2 GHz with an adjustable bandwidth of up to 1.75 GHz are achieved while maintaining low phase noise of −140 dBc/Hz at 1 MHz from the carrier at the center frequency. Synchronous programming and modulation of the fractional frequency divider is done by a new type of control utilizing fast transceivers in a field-programmable gate array (FPGA), which does not require back-synchronization to the frequency divider. Measurements with the novel reference frequency chirp generator combined with a V-band PLL reveal a low RMS linearity error of 0.67ppm of the reference chirp for a chirp duration of 1 ms and a bandwidth of 363 MHz.
{"title":"An Ultra-Wideband Reference Frequency Chirp Generator Utilizing Fractional Frequency Divider With High Linearity","authors":"Bent Walther;Lukas Polzin;Marcel van Delden;Thomas Musch","doi":"10.1109/OJCAS.2024.3409747","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3409747","url":null,"abstract":"Using physically separated multiple-input multiple-output (MIMO) systems for millimeter-wave measurement systems based on linear frequency chirps poses unique challenges for generating a modulated reference chirp to apply high coherence. The reference frequency chirp is crucial for the measurement accuracy of the overall system and should feature high bandwidth, low phase noise, and high linearity. For this reason, we present a novel architecture combining a fixed-integer phase-locked loop (PLL) with a fast-modulated frequency divider. Thus, modulated output frequencies of up to 2 GHz with an adjustable bandwidth of up to 1.75 GHz are achieved while maintaining low phase noise of −140 dBc/Hz at 1 MHz from the carrier at the center frequency. Synchronous programming and modulation of the fractional frequency divider is done by a new type of control utilizing fast transceivers in a field-programmable gate array (FPGA), which does not require back-synchronization to the frequency divider. Measurements with the novel reference frequency chirp generator combined with a V-band PLL reveal a low RMS linearity error of 0.67ppm of the reference chirp for a chirp duration of 1 ms and a bandwidth of 363 MHz.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2024-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10549958","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141495214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-05DOI: 10.1109/OJCAS.2024.3410020
Jeremy Cosson-Martin;Jhoan Salinas;Hossein Shakiba;Ali Sheikholeslami
This paper demonstrates the first silicon-verified FBMC encoder and decoder designed to emulate beyond $224Gb/s$ wireline communication. It also compares the performance of FBMC to PAM and DMT in three steps. First, the digital power and area consumption are compared using measured results from the manufactured test chip. Second, the data rate is determined using lab-measured results. And third, the performance when subject to notched channels is analyzed using simulation results. Finally, we present a method to emulate wireline links while reducing the emulator complexity and simulation time by one to two orders of magnitude over conventional over-sampled techniques. Our analysis indicates that given a smooth channel and an SNR which enables an average spectral efficiency of $4bits/sec/Hz$ at a bit-error rate of 10-3, both DMT and FBMC perform similarly to a conventional PAM-4 link. However, when noise is reduced and a spectral notch is applied, thereby achieving an average spectral efficiency of $4.6bits/sec/Hz$ , DMT and FBMC can outperform PAM by 2.1 and 2.3 times, respectively. In addition, we estimate FBMC’s encoder and decoder power consumption at $1.53pJ/b$ and $1.98pJ/b$ , respectively, and area requirement at $0.07mm^{2}$ and $0.17mm^{2}$ , respectively, which is similar to DMT. These values are competitive with similar $22nm$ PAM transceivers, suggesting that DMT and FBMC are viable alternatives to PAM for next-generation high-speed wireline applications.
{"title":"FBMC vs. PAM and DMT for High-Speed Wireline Communication","authors":"Jeremy Cosson-Martin;Jhoan Salinas;Hossein Shakiba;Ali Sheikholeslami","doi":"10.1109/OJCAS.2024.3410020","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3410020","url":null,"abstract":"This paper demonstrates the first silicon-verified FBMC encoder and decoder designed to emulate beyond \u0000<inline-formula> <tex-math>$224Gb/s$ </tex-math></inline-formula>\u0000 wireline communication. It also compares the performance of FBMC to PAM and DMT in three steps. First, the digital power and area consumption are compared using measured results from the manufactured test chip. Second, the data rate is determined using lab-measured results. And third, the performance when subject to notched channels is analyzed using simulation results. Finally, we present a method to emulate wireline links while reducing the emulator complexity and simulation time by one to two orders of magnitude over conventional over-sampled techniques. Our analysis indicates that given a smooth channel and an SNR which enables an average spectral efficiency of \u0000<inline-formula> <tex-math>$4bits/sec/Hz$ </tex-math></inline-formula>\u0000 at a bit-error rate of 10-3, both DMT and FBMC perform similarly to a conventional PAM-4 link. However, when noise is reduced and a spectral notch is applied, thereby achieving an average spectral efficiency of \u0000<inline-formula> <tex-math>$4.6bits/sec/Hz$ </tex-math></inline-formula>\u0000, DMT and FBMC can outperform PAM by 2.1 and 2.3 times, respectively. In addition, we estimate FBMC’s encoder and decoder power consumption at \u0000<inline-formula> <tex-math>$1.53pJ/b$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$1.98pJ/b$ </tex-math></inline-formula>\u0000, respectively, and area requirement at \u0000<inline-formula> <tex-math>$0.07mm^{2}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$0.17mm^{2}$ </tex-math></inline-formula>\u0000, respectively, which is similar to DMT. These values are competitive with similar \u0000<inline-formula> <tex-math>$22nm$ </tex-math></inline-formula>\u0000 PAM transceivers, suggesting that DMT and FBMC are viable alternatives to PAM for next-generation high-speed wireline applications.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2024-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10549936","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141494956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-22DOI: 10.1109/OJCAS.2024.3391829
Byambajav Ragchaa;Liji Wu;Xiangmin Zhang
Battery monitoring integrated circuits (BMIC) employed in the battery management system (BMS) for electric vehicle (EV) application are subjected to rigorous requirements for accuracy, reliability, and safety. This paper presents a design of an 8-cell battery pack monitoring and balancing IC, which can be stacked to monitor and balance a total of 128 cells. The design of battery cell voltage detection is realized by a second order, incremental $Sigma Delta $ ADC with a high-voltage channel multiplexing scheme. The accuracy of cell voltage detection, achieved with a margin of ±10 mV, is confirmed by the test results. In this paper, we aim to enhance the reliability and robustness of the BMIC by implementing fault detection mechanisms within its circuits and incorporating fault recovery functionalities through digital circuits. To meet safety requirements, this paper adheres to the functional safety standard ISO 26262 for road vehicles. The quantitative analysis of hardware architectural metrics for the proposed BMIC demonstrates compliance with ASIL-D requirements for functional safety.
{"title":"A Design of Fault-Tolerant Battery Monitoring IC for Electric Vehicles Complying With ISO 26262","authors":"Byambajav Ragchaa;Liji Wu;Xiangmin Zhang","doi":"10.1109/OJCAS.2024.3391829","DOIUrl":"10.1109/OJCAS.2024.3391829","url":null,"abstract":"Battery monitoring integrated circuits (BMIC) employed in the battery management system (BMS) for electric vehicle (EV) application are subjected to rigorous requirements for accuracy, reliability, and safety. This paper presents a design of an 8-cell battery pack monitoring and balancing IC, which can be stacked to monitor and balance a total of 128 cells. The design of battery cell voltage detection is realized by a second order, incremental \u0000<inline-formula> <tex-math>$Sigma Delta $ </tex-math></inline-formula>\u0000 ADC with a high-voltage channel multiplexing scheme. The accuracy of cell voltage detection, achieved with a margin of ±10 mV, is confirmed by the test results. In this paper, we aim to enhance the reliability and robustness of the BMIC by implementing fault detection mechanisms within its circuits and incorporating fault recovery functionalities through digital circuits. To meet safety requirements, this paper adheres to the functional safety standard ISO 26262 for road vehicles. The quantitative analysis of hardware architectural metrics for the proposed BMIC demonstrates compliance with ASIL-D requirements for functional safety.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10506220","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140635283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-19DOI: 10.1109/OJCAS.2024.3391698
Mohammad Emami Meybodi;Hossein Shakiba;Ali Sheikholeslami
This paper presents a comprehensive study of noise prediction and cancellation techniques in high-speed wireline communication systems. Feedforward and feedback architectures are compared, and it is found that while feedforward architecture can reduce total noise power, it fails to reduce symbol error rate (SER) due to unreliable noise estimation. To address this issue, an optimal noise estimation and cancellation filter (ONECF) is proposed, which directly minimizes SER. The paper provides mathematical analysis and experimental results of ONECF, demonstrating that ONECF is effective in reducing SER and improving SNR, and the degree of improvement is proportional to the channel loss. However, ONECF’s performance saturates at a certain level, which depends on the number of taps used. We conclude that feedforward noise cancelling filters are suitable for low to medium loss channels, whereas feedback ones are suitable for high loss channels.
本文全面研究了高速有线通信系统中的噪声预测和消除技术。比较了前馈和反馈架构，发现前馈架构虽然能降低总噪声功率，但由于噪声估计不可靠，无法降低符号错误率（SER）。为了解决这个问题，本文提出了一种最优噪声估计和消除滤波器（ONECF），它能直接将 SER 降到最低。论文提供了 ONECF 的数学分析和实验结果，证明 ONECF 能有效降低 SER 并提高 SNR，而且改善程度与信道损耗成正比。然而，ONECF 的性能会在一定程度上达到饱和，这取决于所使用的抽头数量。我们的结论是，前馈噪声消除滤波器适用于中低损耗信道，而反馈滤波器适用于高损耗信道。
{"title":"Analysis and Design of an Optimal Noise Estimation and Cancellation Filter in Wireline Communication","authors":"Mohammad Emami Meybodi;Hossein Shakiba;Ali Sheikholeslami","doi":"10.1109/OJCAS.2024.3391698","DOIUrl":"10.1109/OJCAS.2024.3391698","url":null,"abstract":"This paper presents a comprehensive study of noise prediction and cancellation techniques in high-speed wireline communication systems. Feedforward and feedback architectures are compared, and it is found that while feedforward architecture can reduce total noise power, it fails to reduce symbol error rate (SER) due to unreliable noise estimation. To address this issue, an optimal noise estimation and cancellation filter (ONECF) is proposed, which directly minimizes SER. The paper provides mathematical analysis and experimental results of ONECF, demonstrating that ONECF is effective in reducing SER and improving SNR, and the degree of improvement is proportional to the channel loss. However, ONECF’s performance saturates at a certain level, which depends on the number of taps used. We conclude that feedforward noise cancelling filters are suitable for low to medium loss channels, whereas feedback ones are suitable for high loss channels.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10505903","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140626387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
During snowfall, the utility of the road infrastructure is critical. Roads must be effectively cleared to ensure access to important locations and services. In this paper, we present an end-to-end framework for snow removal vehicle routing based on road priority. We offer an artificial intelligence-based image-based approach for estimating snow depth and traffic volume on roads. For segments monitored by CCTV cameras, we exploit images and supervised learning models to perform this task. For unmonitored roads, we use the Graph Convolutional Network architecture to predict parameters in a semi-supervised manner. Following that, we assign priority weights to all graph edges as a function of image-based attributes and road categories. We test the method using a real-world example, simulating snow removal within a study area in Montreal, Quebec, Canada. As input for the framework, we collect CCTV image data and combine it with a 2D map. As a result, more efficient snow removal operation can be achieved by optimizing the trajectories of trucks based on the computer vision module outputs.
{"title":"A Computer Vision-Based Framework for Snow Removal Operation Routing","authors":"Mohamed Karaa;Hakim Ghazzai;Yehia Massoud;Lokman Sboui","doi":"10.1109/OJCAS.2023.3326274","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3326274","url":null,"abstract":"During snowfall, the utility of the road infrastructure is critical. Roads must be effectively cleared to ensure access to important locations and services. In this paper, we present an end-to-end framework for snow removal vehicle routing based on road priority. We offer an artificial intelligence-based image-based approach for estimating snow depth and traffic volume on roads. For segments monitored by CCTV cameras, we exploit images and supervised learning models to perform this task. For unmonitored roads, we use the Graph Convolutional Network architecture to predict parameters in a semi-supervised manner. Following that, we assign priority weights to all graph edges as a function of image-based attributes and road categories. We test the method using a real-world example, simulating snow removal within a study area in Montreal, Quebec, Canada. As input for the framework, we collect CCTV image data and combine it with a 2D map. As a result, more efficient snow removal operation can be achieved by optimizing the trajectories of trucks based on the computer vision module outputs.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10500496","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140559271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Approximate computing is an emerging and effective method for reducing energy consumption in digital circuits, which is critical for energy-efficient performance improvement of edge-computing devices. In this paper, we propose a low-power DNN accelerator with novel signed approximate multiplier based on probability-optimized compressor and error compensation. The probability-optimized compressor is customized for partial product matrix (PPM) of signed operands, which gets the optimal logic circuit after probabilistic analysis and optimization. At the same time, we explored the PPM truncation method, found out the impact of different partial product (PP) truncation numbers on circuit benefit and error, and achieved a more ideal performance-error tradeoff through a reasonable error compensation method. In the optimal case of 8 bits, the proposed approximate multiplier saves 49.84% power, 46.41% area and 24.65% delay compared to the exact multiplier. We employed the proposed approximate multiplier in the vector systolic array as the processing element (PE). Under the VGG-16 evaluation, the proposed accelerator achieves performance improvement of energy efficiency $1.96times $ , while the error loss was only 0.95%.
{"title":"A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier","authors":"Laimin Du;Leibin Ni;Xiong Liu;Guanqi Peng;Kai Li;Wei Mao;Hao Yu","doi":"10.1109/OJCAS.2023.3279251","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3279251","url":null,"abstract":"Approximate computing is an emerging and effective method for reducing energy consumption in digital circuits, which is critical for energy-efficient performance improvement of edge-computing devices. In this paper, we propose a low-power DNN accelerator with novel signed approximate multiplier based on probability-optimized compressor and error compensation. The probability-optimized compressor is customized for partial product matrix (PPM) of signed operands, which gets the optimal logic circuit after probabilistic analysis and optimization. At the same time, we explored the PPM truncation method, found out the impact of different partial product (PP) truncation numbers on circuit benefit and error, and achieved a more ideal performance-error tradeoff through a reasonable error compensation method. In the optimal case of 8 bits, the proposed approximate multiplier saves 49.84% power, 46.41% area and 24.65% delay compared to the exact multiplier. We employed the proposed approximate multiplier in the vector systolic array as the processing element (PE). Under the VGG-16 evaluation, the proposed accelerator achieves performance improvement of energy efficiency \u0000<inline-formula> <tex-math>$1.96times $ </tex-math></inline-formula>\u0000, while the error loss was only 0.95%.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10500495","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140559367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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