Pub Date : 2025-12-10DOI: 10.1109/OJCAS.2025.3532762
Li You;Liangli Xiong;Gang Han;Sheng Zhang;Zhijian Fang
Grid type energy storage has inertia support capability, and unbalanced grid voltage will cause grid type energy storage current fluctuation and active power fluctuation. In this paper, a control method for unbalanced current in grid type energy storage based on negative sequence virtual impedance is proposed, analyze the reasons for the fluctuation of grid type energy storage current, and adopts the inner-loop positive-negative sequence separation control method, adding virtual impedance to suppress the negative sequence current only in the negative sequence control loop. And the relationship between the virtual impedance values and system stability in the background of grid harmonics are analyzed. Finally, simulations and experiments show that the addition of virtual impedance only in negative sequence does not affect the normal operating conditions, but has the characteristic of producing effects under unbalanced grid voltage. The method is simple to implement and the output current and active power fluctuations of the grid type energy storage are effectively suppressed.
{"title":"A Control Method for Unbalanced Current in Grid Type Energy Storage Based on Negative Sequence Virtual Impedance","authors":"Li You;Liangli Xiong;Gang Han;Sheng Zhang;Zhijian Fang","doi":"10.1109/OJCAS.2025.3532762","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3532762","url":null,"abstract":"Grid type energy storage has inertia support capability, and unbalanced grid voltage will cause grid type energy storage current fluctuation and active power fluctuation. In this paper, a control method for unbalanced current in grid type energy storage based on negative sequence virtual impedance is proposed, analyze the reasons for the fluctuation of grid type energy storage current, and adopts the inner-loop positive-negative sequence separation control method, adding virtual impedance to suppress the negative sequence current only in the negative sequence control loop. And the relationship between the virtual impedance values and system stability in the background of grid harmonics are analyzed. Finally, simulations and experiments show that the addition of virtual impedance only in negative sequence does not affect the normal operating conditions, but has the characteristic of producing effects under unbalanced grid voltage. The method is simple to implement and the output current and active power fluctuations of the grid type energy storage are effectively suppressed.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"477-486"},"PeriodicalIF":2.4,"publicationDate":"2025-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11293418","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145729375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-09DOI: 10.1109/OJCAS.2025.3541626
Zhiheng Zhao;Jinhong Sun
Magnetically Coupled Wireless Power Transfer (MC-WPT) technology offers wire-free power delivery with advantages in safety, convenience, and adaptability across various power levels and transmission distances. However, traditional single-output MC-WPT systems are inadequate for the increasing demand to supply power simultaneously to multiple devices with diverse voltage requirements. This paper proposes two voltage output techniques for MC-WPT systems: a Single Transmitter coil and Double Receiver coils (STDR) method with high offset tolerance. The STDR approach employs a receiver-side decoupling coupling mechanism optimized via finite element analysis (FEA), achieving stable dual voltage outputs of 36 V with voltage fluctuations under 28.6% across ±50 mm X-axis offsets. Experimental results validate that the proposed system maintain constant voltage outputs under input or load perturbations, demonstrating their effectiveness and practicality for double-output MC-WPT applications.
磁耦合无线电力传输（MC-WPT）技术在各种功率水平和传输距离上提供安全、方便和适应性的无线电力传输。然而，传统的单输出MC-WPT系统已不足以满足不断增长的同时为具有不同电压要求的多个设备供电的需求。本文提出了两种用于MC-WPT系统的电压输出技术：单发送线圈和双接收线圈（STDR）方法，具有高偏移容限。STDR方法采用经有限元分析（FEA）优化的接收端去耦耦合机制，实现了36 V的稳定双电压输出，在±50 mm x轴偏移范围内电压波动小于28.6%。实验结果验证了该系统在输入或负载扰动下保持恒定电压输出，证明了其在双输出MC-WPT应用中的有效性和实用性。
{"title":"Double-Channel Constant Voltage Output Design in Magnetically Coupled Wireless Power Transfer Systems With the Anti-Misalignment Capability","authors":"Zhiheng Zhao;Jinhong Sun","doi":"10.1109/OJCAS.2025.3541626","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3541626","url":null,"abstract":"Magnetically Coupled Wireless Power Transfer (MC-WPT) technology offers wire-free power delivery with advantages in safety, convenience, and adaptability across various power levels and transmission distances. However, traditional single-output MC-WPT systems are inadequate for the increasing demand to supply power simultaneously to multiple devices with diverse voltage requirements. This paper proposes two voltage output techniques for MC-WPT systems: a Single Transmitter coil and Double Receiver coils (STDR) method with high offset tolerance. The STDR approach employs a receiver-side decoupling coupling mechanism optimized via finite element analysis (FEA), achieving stable dual voltage outputs of 36 V with voltage fluctuations under 28.6% across ±50 mm X-axis offsets. Experimental results validate that the proposed system maintain constant voltage outputs under input or load perturbations, demonstrating their effectiveness and practicality for double-output MC-WPT applications.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"496-503"},"PeriodicalIF":2.4,"publicationDate":"2025-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11286039","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145729294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-09DOI: 10.1109/OJCAS.2025.3531412
U Chi-Wa;Zhaoxi Li;Cheng-Hou Cheong;Chon-Fai Lee;Chi-Seng Lam
This paper presents a bandgap voltage reference (BGR) circuit with a wide supply voltage and temperature range, suitable for automotive applications. We use multi-objective artificial intelligence (AI) optimization to improve both the temperature coefficient (TC) and line regulation simultaneously ensuring VREF accuracy over a wide temperature and supply voltage range. The design uses a lateral double-diffused MOS (LDMOS) transistor to handle high-voltage stress. To extend the operating temperature range, we use low-power quasi-beta compensation. A regulated-cascode current mirror minimizes errors from current replication, enhancing the TC. Fabricated in 180nm BCD, results from 10-chip measurements show an average TC of 44.9 ppm/°C at a 2.0V supply, within the range of -40°C to 150°C. Line regulation measures 0.13 mV/V or 0.0144%/V from 2V to 12V across the entire temperature range.
{"title":"AI-Enhanced Wide Supply Voltage Bandgap Voltage Reference Circuit With Multi-Objective Optimization for Automotive Applications","authors":"U Chi-Wa;Zhaoxi Li;Cheng-Hou Cheong;Chon-Fai Lee;Chi-Seng Lam","doi":"10.1109/OJCAS.2025.3531412","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3531412","url":null,"abstract":"This paper presents a bandgap voltage reference (BGR) circuit with a wide supply voltage and temperature range, suitable for automotive applications. We use multi-objective artificial intelligence (AI) optimization to improve both the temperature coefficient (TC) and line regulation simultaneously ensuring VREF accuracy over a wide temperature and supply voltage range. The design uses a lateral double-diffused MOS (LDMOS) transistor to handle high-voltage stress. To extend the operating temperature range, we use low-power quasi-beta compensation. A regulated-cascode current mirror minimizes errors from current replication, enhancing the TC. Fabricated in 180nm BCD, results from 10-chip measurements show an average TC of 44.9 ppm/°C at a 2.0V supply, within the range of -40°C to 150°C. Line regulation measures 0.13 mV/V or 0.0144%/V from 2V to 12V across the entire temperature range.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"487-495"},"PeriodicalIF":2.4,"publicationDate":"2025-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11286137","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145729301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-09DOI: 10.1109/OJCAS.2025.3535919
Osarodion Emmanuel Egbomwan;Shichao Liu;Hicham Chaoui;Xiaozhe Wang
The increasing integration of renewable energy generators into the conventional power grid has lowered the overall power system inertia. Low inertia may adversely impact the grid’s stability and resilience, leading to unintended grid failure and total system collapse upon severe contingencies. Current methods of emulating power grid inertia to enhance stability under low inertia conditions have some drawbacks. For example, the proportional-integral (PI) control method suffers from high overshoot and settling time, while the performance of the conventional model predictive controller (MPC) is highly dependent on the accuracy of the system model. Consequently, a new learning-based predictive virtual inertia control (VIC) is proposed. This strategy incorporates a physics-informed neural network (PINN) predictive model with an optimization-based safety filter to mitigate the impact of increasing integration of renewable energy generators through a virtual inertia emulation strategy. Our proposed strategy leverages advances in deep learning by implementing a PINN-based model to predict the system’s future behavior. The proposed method is compared to the MPC and PI controller. The results demonstrate the superior dynamic performance of the proposed method. Our implemented technique achieved the least frequency deviations upon contingencies in the IEEE 34 bus and the IEEE 39 bus studied systems with integrated inverter-based generators.
{"title":"Learning-Based Predictive Virtual Inertia Control for Frequency Regulation in Low Inertia Power Grids","authors":"Osarodion Emmanuel Egbomwan;Shichao Liu;Hicham Chaoui;Xiaozhe Wang","doi":"10.1109/OJCAS.2025.3535919","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3535919","url":null,"abstract":"The increasing integration of renewable energy generators into the conventional power grid has lowered the overall power system inertia. Low inertia may adversely impact the grid’s stability and resilience, leading to unintended grid failure and total system collapse upon severe contingencies. Current methods of emulating power grid inertia to enhance stability under low inertia conditions have some drawbacks. For example, the proportional-integral (PI) control method suffers from high overshoot and settling time, while the performance of the conventional model predictive controller (MPC) is highly dependent on the accuracy of the system model. Consequently, a new learning-based predictive virtual inertia control (VIC) is proposed. This strategy incorporates a physics-informed neural network (PINN) predictive model with an optimization-based safety filter to mitigate the impact of increasing integration of renewable energy generators through a virtual inertia emulation strategy. Our proposed strategy leverages advances in deep learning by implementing a PINN-based model to predict the system’s future behavior. The proposed method is compared to the MPC and PI controller. The results demonstrate the superior dynamic performance of the proposed method. Our implemented technique achieved the least frequency deviations upon contingencies in the IEEE 34 bus and the IEEE 39 bus studied systems with integrated inverter-based generators.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"504-519"},"PeriodicalIF":2.4,"publicationDate":"2025-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11286041","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145729356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-02DOI: 10.1109/OJCAS.2025.3639222
Tianshu Liu;Tao Zhang;Yukan Du;Wanyuan Qu
This paper introduces a fully integrated 4-phase 16-channel Buck converter capable of delivering up to 50A of current with a vertical power delivery structure. The converter employs a delay-line-based pulse-width modulation scheme, which ensures decent duty cycle matching across all phases. To further enhance performance, an accurate high-speed full-wave current sensor and a current-balance feedback loop are incorporated to actively regulate and balance current distribution among all 16 channels. Furthermore, substrate metals are adopted to implement the vertical 3D air-core inductors to verify the proposed vertical power delivery. Fabricated in 28nm CMOS technology, the prototype achieves a peak efficiency of 87% and supports a maximum load current of 50A, with an impressive die-area current density of 5.14A/mm2. Under a 50MHz switching frequency, the converter exhibits a measured bandwidth of 7.1MHz and a phase margin of 55°, demonstrating robust stability. The worst-case average current imbalance across all phases is limited to 10.7% over the full load range. These results indicate that the proposed design is highly suitable for high-density power management in advanced multi-core System-on-Chips (SoCs).
{"title":"A 30-70MHz Delay-Line-Based Multiphase 50A 5.14 A/mm² Fully Integrated Voltage Regulator","authors":"Tianshu Liu;Tao Zhang;Yukan Du;Wanyuan Qu","doi":"10.1109/OJCAS.2025.3639222","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3639222","url":null,"abstract":"This paper introduces a fully integrated 4-phase 16-channel Buck converter capable of delivering up to 50A of current with a vertical power delivery structure. The converter employs a delay-line-based pulse-width modulation scheme, which ensures decent duty cycle matching across all phases. To further enhance performance, an accurate high-speed full-wave current sensor and a current-balance feedback loop are incorporated to actively regulate and balance current distribution among all 16 channels. Furthermore, substrate metals are adopted to implement the vertical 3D air-core inductors to verify the proposed vertical power delivery. Fabricated in 28nm CMOS technology, the prototype achieves a peak efficiency of 87% and supports a maximum load current of 50A, with an impressive die-area current density of 5.14A/mm2. Under a 50MHz switching frequency, the converter exhibits a measured bandwidth of 7.1MHz and a phase margin of 55°, demonstrating robust stability. The worst-case average current imbalance across all phases is limited to 10.7% over the full load range. These results indicate that the proposed design is highly suitable for high-density power management in advanced multi-core System-on-Chips (SoCs).","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"520-529"},"PeriodicalIF":2.4,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11271853","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-25DOI: 10.1109/OJCAS.2025.3581188
Rella Mareta;Ardianto Satriawan;Hanho Lee
Homomorphic Encryption (HE) enables secure computations on encrypted data, which is crucial for cloud and edge computing. The BFV scheme, widely used for integer arithmetic, faces performance bottlenecks in polynomial multiplication, especially in tensor operations. The Residue Number System (RNS) helps address this, leading to the BEHZ and HPS BFV variants. The Halevi-Polyakov-Shoup (HPS) variant simplifies implementation but still struggles with the overhead of modular arithmetic. We propose an Arithmetic Computing Unit (ACU) optimized for key BFV operations, including modular addition, multiplication, NTT/INTT, and MAC to improve efficiency. Implemented on a Xilinx Alveo U250 FPGA, our design achieves up to $2.3{times }$ higher throughput, $2.2{times }$ less latency, and $9.4{times }$ better BRAM efficiency than existing solutions, demonstrating FPGA acceleration’s for homomorphic encryption.
{"title":"High Throughput Arithmetic Computing Unit for BFV Homomorphic Encryption","authors":"Rella Mareta;Ardianto Satriawan;Hanho Lee","doi":"10.1109/OJCAS.2025.3581188","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3581188","url":null,"abstract":"Homomorphic Encryption (HE) enables secure computations on encrypted data, which is crucial for cloud and edge computing. The BFV scheme, widely used for integer arithmetic, faces performance bottlenecks in polynomial multiplication, especially in tensor operations. The Residue Number System (RNS) helps address this, leading to the BEHZ and HPS BFV variants. The Halevi-Polyakov-Shoup (HPS) variant simplifies implementation but still struggles with the overhead of modular arithmetic. We propose an Arithmetic Computing Unit (ACU) optimized for key BFV operations, including modular addition, multiplication, NTT/INTT, and MAC to improve efficiency. Implemented on a Xilinx Alveo U250 FPGA, our design achieves up to <inline-formula> <tex-math>$2.3{times }$ </tex-math></inline-formula> higher throughput, <inline-formula> <tex-math>$2.2{times }$ </tex-math></inline-formula> less latency, and <inline-formula> <tex-math>$9.4{times }$ </tex-math></inline-formula> better BRAM efficiency than existing solutions, demonstrating FPGA acceleration’s for homomorphic encryption.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"457-466"},"PeriodicalIF":2.4,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11267476","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145612056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-25DOI: 10.1109/OJCAS.2025.3589132
M. Ajay Kumar;Cian O’Mahoney;Pedro Kreutz Werle;Shreejith Shanker;Dimitrios S. Nikolopoulos;Bo Ji;Hans Vandierendonck;Deepu John
Deploying deep neural networks (DNNs) on resource-constrained IoT devices remains a challenging problem, often requiring hardware modifications tailored to individual AI models. Existing accelerator-generation tools, such as AMD’s FINN, do not adequately address extreme resource limitations faced by IoT endpoints operating in bare-metal environments without an operating system (OS). To overcome these constraints, we propose MARVEL–an automated, end-to-end framework that generates custom RISC-V ISA extensions tailored to specific DNN model classes, with a primary focus on convolutional neural networks (CNNs). The proposed method profiles high-level DNN representations in Python and generates an ISA-extended RISC-V core with associated compiler tools for efficient deployment. The flow leverages (1) Apache TVM for translating high-level Python-based DNN models into optimized C code, (2) Synopsys ASIP Designer for identifying compute-intensive kernels, modeling, and generating a custom RISC-V and (3) Xilinx Vivado for FPGA implementation. Beyond a model-class specific RISC-V, our approach produces an optimized bare-metal C implementation, eliminating the need for an OS or extensive software dependencies. Unlike conventional deployment pipelines relying on TensorFlow/PyTorch runtimes, our solution enables seamless execution in highly resource-constrained environments. We evaluated the flow on popular DNN models such as LeNet-5*, MobileNetV1, ResNet50, VGG16, MobileNetV2 and DenseNet121 using the Synopsys trv32p3 RISC-V core as a baseline. Results show a $2times $ speedup in inference and upto $2times $ reduction in energy per inference at a 28.23% area overhead when implemented on an AMD Zynq UltraScale+ ZCU104 FPGA platform.
{"title":"MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI","authors":"M. Ajay Kumar;Cian O’Mahoney;Pedro Kreutz Werle;Shreejith Shanker;Dimitrios S. Nikolopoulos;Bo Ji;Hans Vandierendonck;Deepu John","doi":"10.1109/OJCAS.2025.3589132","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3589132","url":null,"abstract":"Deploying deep neural networks (DNNs) on resource-constrained IoT devices remains a challenging problem, often requiring hardware modifications tailored to individual AI models. Existing accelerator-generation tools, such as AMD’s FINN, do not adequately address extreme resource limitations faced by IoT endpoints operating in bare-metal environments without an operating system (OS). To overcome these constraints, we propose MARVEL–an automated, end-to-end framework that generates custom RISC-V ISA extensions tailored to specific DNN model classes, with a primary focus on convolutional neural networks (CNNs). The proposed method profiles high-level DNN representations in Python and generates an ISA-extended RISC-V core with associated compiler tools for efficient deployment. The flow leverages (1) Apache TVM for translating high-level Python-based DNN models into optimized C code, (2) Synopsys ASIP Designer for identifying compute-intensive kernels, modeling, and generating a custom RISC-V and (3) Xilinx Vivado for FPGA implementation. Beyond a model-class specific RISC-V, our approach produces an optimized bare-metal C implementation, eliminating the need for an OS or extensive software dependencies. Unlike conventional deployment pipelines relying on TensorFlow/PyTorch runtimes, our solution enables seamless execution in highly resource-constrained environments. We evaluated the flow on popular DNN models such as LeNet-5*, MobileNetV1, ResNet50, VGG16, MobileNetV2 and DenseNet121 using the Synopsys trv32p3 RISC-V core as a baseline. Results show a <inline-formula> <tex-math>$2times $ </tex-math></inline-formula> speedup in inference and upto <inline-formula> <tex-math>$2times $ </tex-math></inline-formula> reduction in energy per inference at a 28.23% area overhead when implemented on an AMD Zynq UltraScale+ ZCU104 FPGA platform.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"445-456"},"PeriodicalIF":2.4,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11267280","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145612055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-27DOI: 10.1109/OJCAS.2025.3625587
Ruoman Yang;Tzu-Chien Hsueh
A low-power time-to-voltage converter (TVC) is composed of a reconfigurable current-mode integrator and a capacitive voltage holder specifically for random sampling-and-averaging (RSA) time-to-digital conversions (TDC) in time-correlated single-photon counting (TCSPC) systems. To accommodate the TVC circuit within each single-photon detection pixel for compact silicon-photonics integration, this paper exploits the Miller-impedance technique to demonstrate the leakage time-constant of the voltage holder being extended up to tens of milliseconds, which represents a more than $100times $ improvement in high-leakage 22-nm digital CMOS process technology, with only a 9-pF (36-$mu $ m $times 36$ -$mu $ m) metal-finger hold capacitor and 120-$mu $ W power consumption.
针对时间相关单光子计数（TCSPC）系统中的随机采样和平均（RSA）时间-数字转换（TDC），设计了一种低功耗时间-电压转换器（TVC），由可重构电流模式积分器和电容电压保持器组成。为了在每个单光子检测像素内容纳TVC电路以实现紧凑的硅光子集成，本文利用米勒阻抗技术证明了电压保持器的泄漏时间常数被扩展到数十毫秒，这代表了高泄漏22纳米数字CMOS工艺技术的100多倍改进。只有一个9-pF （36- $mu $ m $乘以36$ - $mu $ m $）金属手指保持电容器和120- $mu $ W的功耗。
{"title":"A Time-to-Voltage Converter With Miller-Impedance Technique for Single-Photon Arrival Time-to-Digital Conversions","authors":"Ruoman Yang;Tzu-Chien Hsueh","doi":"10.1109/OJCAS.2025.3625587","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3625587","url":null,"abstract":"A low-power time-to-voltage converter (TVC) is composed of a reconfigurable current-mode integrator and a capacitive voltage holder specifically for random sampling-and-averaging (RSA) time-to-digital conversions (TDC) in time-correlated single-photon counting (TCSPC) systems. To accommodate the TVC circuit within each single-photon detection pixel for compact silicon-photonics integration, this paper exploits the Miller-impedance technique to demonstrate the leakage time-constant of the voltage holder being extended up to tens of milliseconds, which represents a more than <inline-formula> <tex-math>$100times $ </tex-math></inline-formula> improvement in high-leakage 22-nm digital CMOS process technology, with only a 9-pF (36-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m <inline-formula> <tex-math>$times 36$ </tex-math></inline-formula>-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m) metal-finger hold capacitor and 120-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W power consumption.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"467-476"},"PeriodicalIF":2.4,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11218226","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145674774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-05DOI: 10.1109/OJCAS.2025.3606618
Paul Kaesser;Maurits Ortmanns
incremental Delta-Sigma (I-DS) analog-to-digital converters (ADCs) are widely utilized in applications requiring high-resolution Nyquist conversion. Accurate performance prediction of these converters is crucial for efficient design and optimization. Existing state of the art (SoA) equations are either lacking sufficient accuracy or simplicity in predicting quantization noise performance under various architectural scenarios. This paper reviews the derivation and limitations of existing performance prediction models. A more general and accurate analysis is derived for predicting the performance of I-DS ADCs, addressing the shortcomings of the conventional approaches. The validity of the proposed performance prediction is rigorously evaluated through extensive simulations across a broad range of architectural choices. The results establish the new model as a robust tool for predicting the performance of I-DS ADCs, advancing the SoA, and facilitating more effective design strategies in the field.
{"title":"Performance Prediction of Incremental ΔΣ ADCs","authors":"Paul Kaesser;Maurits Ortmanns","doi":"10.1109/OJCAS.2025.3606618","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3606618","url":null,"abstract":"incremental Delta-Sigma (I-DS) analog-to-digital converters (ADCs) are widely utilized in applications requiring high-resolution Nyquist conversion. Accurate performance prediction of these converters is crucial for efficient design and optimization. Existing state of the art (SoA) equations are either lacking sufficient accuracy or simplicity in predicting quantization noise performance under various architectural scenarios. This paper reviews the derivation and limitations of existing performance prediction models. A more general and accurate analysis is derived for predicting the performance of I-DS ADCs, addressing the shortcomings of the conventional approaches. The validity of the proposed performance prediction is rigorously evaluated through extensive simulations across a broad range of architectural choices. The results establish the new model as a robust tool for predicting the performance of I-DS ADCs, advancing the SoA, and facilitating more effective design strategies in the field.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"424-431"},"PeriodicalIF":2.4,"publicationDate":"2025-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11152582","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145110271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-03DOI: 10.1109/OJCAS.2025.3604902
Uday Maurya;Mahima Arrawatia;Nagarjuna Nallam
The balanced power amplifier (BPA) topology is commonly used in applications requiring high antenna impedance tolerance. This paper presents a low-loss transmit-receive (T/R) front-end module (FEM) with BPA using four shunt switches. These switches are embedded into the output network of the BPA and the input matching network of the common source low noise amplifier (LNA). A prototype T/R FEM is implemented in bulk CMOS 65 nm technology for the 5G FR2 n260 band. As per simulations, the extra loss due to the T/R interface in transmit mode is 0.75 dB, and the noise figure (NF) degradation in receive mode is 1.5 dB. The prototype chip is characterized by die-probing. The BPA delivers a saturated power output of + 18 dBm with a power-added efficiency (PAE) of 14.5 % at 40 GHz in measurements. The LNA has a gain of 21.3 dB and a noise figure of 5.8 dB in the n260 band.
{"title":"A Low-Loss T/R Module With Balanced Power Amplifier for High Antenna Impedance Tolerance","authors":"Uday Maurya;Mahima Arrawatia;Nagarjuna Nallam","doi":"10.1109/OJCAS.2025.3604902","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3604902","url":null,"abstract":"The balanced power amplifier (BPA) topology is commonly used in applications requiring high antenna impedance tolerance. This paper presents a low-loss transmit-receive (T/R) front-end module (FEM) with BPA using four shunt switches. These switches are embedded into the output network of the BPA and the input matching network of the common source low noise amplifier (LNA). A prototype T/R FEM is implemented in bulk CMOS 65 nm technology for the 5G FR2 n260 band. As per simulations, the extra loss due to the T/R interface in transmit mode is 0.75 dB, and the noise figure (NF) degradation in receive mode is 1.5 dB. The prototype chip is characterized by die-probing. The BPA delivers a saturated power output of + 18 dBm with a power-added efficiency (PAE) of 14.5 % at 40 GHz in measurements. The LNA has a gain of 21.3 dB and a noise figure of 5.8 dB in the n260 band.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"414-423"},"PeriodicalIF":2.4,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11150516","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：