Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization

In this paper, it is proposed a jitter analysis methodology, targeting on the optimization of a phase interpolator (PI) based clock and data recovery circuit (CDR). The methodology is applied for the optimized design of an 8-bit dual-loop CDR, designed with the CMOS TSMC 65 nm process node. The CDR is based on an extended, in terms of phase resolution, version, with a novel PI topology proposed in this work. The proposed CDR loop has a minimum frequency offset tracking ability equal to 500ppm at 5.83 Gbps, and so is suitable for adoption either in mesochronous or plesiochronous High Speed Serial Interface (HSSI) receivers. It consumes 14.2 mW with 1 V supply voltage and is able to achieve better than 10−10 Bit Error Rate (BER) performance. The CDR loop performance verification has been realized through the AMS simulator of Analog Design Environment of Cadence, by co-simulations of the transistor level CDR circuit with the Verilog-AMS based jitter generator.