高效分布式DNN训练的快速性能预测

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2023-09-18 DOI:10.1109/LCA.2023.3316452
Yugyoung Yun;Eunhyeok Park
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引用次数: 0

摘要

训练大规模DNN模型需要使用超大规模系统进行并行分布式训练。为了充分利用众多的加速器,必须智能地组合不同的并行化方案。然而,随着深度神经网络模型规模的增加,可能的方案组合变得非常庞大,因此,找到最优的并行方案变得非常昂贵,实际上是不可行的。在这封信中,我们介绍了一个新的成本模型,马尔可夫性能估计(MPE)。该模型提供了各种并行计划的可负担的吞吐量估计,即使在资源有限的情况下,也可以促进对理想并行计划的高效和快速搜索。值得注意的是,这项工作开创性地解释了寻找最佳计划的昂贵性质,并使用基于真实设备评估的直观性能估计来解决它。我们的实验证明了MPE的有效性,表明它比现有的最先进的基线Alpa加速了优化过程,速度提高了126倍(平均36.4)。
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Fast Performance Prediction for Efficient Distributed DNN Training
Training large-scale DNN models requires parallel distributed training using hyper-scale systems. To make the best use of the numerous accelerators, it is essential to intelligently combine different parallelization schemes. However, as the size of DNN models increases, the possible combinations of schemes become enormous, and consequently, finding the optimal parallel plan becomes exceedingly expensive and practically unfeasible. In this letter, we introduce a novel cost model, the Markovian Performance Estimator (MPE). This model provides affordable estimates of the throughput of various parallel plans, promoting efficient and fast searches for the ideal parallel plan, even when resources are limited. Significantly, this work is pioneering in explaining the expensive nature of searching for an optimal plan and addressing it using intuitive performance estimations based on real device evaluations. Our experiments demonstrate the effectiveness of the MPE, revealing that it accelerates the optimization process up to 126x faster (36.4 on average) than the existing state-of-the-art baseline, Alpa.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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