Jiawei Wang, Hao Xu, Ziqiang Wang, Haikun Jia, Hanjun Jiang, Chun Zhang, Zhihua Wang
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A 128 Gbps PAM-4 feed forward equaliser with optimized 1UI pulse generator in 65 nm CMOS
A quarter-rate PAM-4 FFE employing INCC 1UIPG is implemented in 65 nm CMOS. The proposed INNC 1UIPG reduces the average transition time by ~20%, saving clocking power consumption by ~1.5X, lowering jitter amplification by about 2~5 dB compared with previous works. Along with the bandwidth- and power-efficient partially segmented tailless 1-stage front-end architecture, the proposed FFE achieves 128Gbps PAM-4 data rate with a 0.014 mm2 area.
期刊介绍：
IET Circuits, Devices & Systems covers the following topics:
Circuit theory and design, circuit analysis and simulation, computer aided design
Filters (analogue and switched capacitor)
Circuit implementations, cells and architectures for integration including VLSI
Testability, fault tolerant design, minimisation of circuits and CAD for VLSI
Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs
Device and process characterisation, device parameter extraction schemes
Mathematics of circuits and systems theory
Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers
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