A CMOS slew-rate controlled output driver with low process, voltage and temperature variations using a dual-path signal-superposition technique

A dual-path open-loop slew-rate (SR) controlled Complementary Metal Oxide Semiconductor (CMOS) driver is presented in this study. The proposed output driver incorporates a delay-locked loop (DLL) to minimise the SR variations over process, voltage and temperature, generating delayed versions of transmitted signal by sampling the input data with adjacent phases of the clock from the DLL. A dual-path open-loop signal-superposition technique is introduced to suppress the high-frequency components of the output driver and thus improves the SR of the CMOS driver. The proposed CMOS output driver achieves a maximum SR of 1.00 and <0.35 V/ns variation operating at 500 Mbps over 32 corners. Both the conventional CMOS driver and the proposed SR controlled output driver were fabricated in a 0.18 μm CMOS process. The proposed driver occupies a compact area of 0.088 mm² and consumes 55.27 mW with a 1.8 V supply voltage. Measurement results show that the SR of the proposed output driver is <0.816 V/ns, corresponding to 62% reduction compared with that of a conventional output driver, and the total jitter is <0.16 unit interval.