多级CMOS放大器的全有源频率补偿分析

Ilghar Rezaei , Amir Ali Mohammad Khani , Morteza Dadgar , Mahdis Attar
{"title":"多级CMOS放大器的全有源频率补偿分析","authors":"Ilghar Rezaei ,&nbsp;Amir Ali Mohammad Khani ,&nbsp;Morteza Dadgar ,&nbsp;Mahdis Attar","doi":"10.1016/j.memori.2023.100068","DOIUrl":null,"url":null,"abstract":"<div><p>An enhanced three-stage CMOS transconductance amplifier attached to a novel frequency compensation network is proposed. Two differential stages are attached with Miller capacitors and the Miller effect is boosted accordingly. In this way, four negative loops intensify the Miller effect virtually. The structure is designed at the transistor level using 0.18 <span><math><mi>μ</mi></math></span>m CMOS library and the SPICE simulator while a symbolical transfer function is extracted and analyzed to obtain circuit dynamics. Leveraging both concept and method, the proposed amplifier shows unconditional stability with acceptable accuracy regarding the symbolic description and simulation results. Ample sensitivity analysis is also provided to show the reliability of the amplifier. By simulation responses, the presented circuit expresses competitive merits against previous works. Simulation results show 120 dB as DC gain, 18 MHz as, GBW, and 54º as phase margin while the simulated amplifier consumes only <span><math><mrow><mn>345</mn><mspace></mspace><mi>μ</mi><mi>W</mi></mrow></math></span>.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"5 ","pages":"Article 100068"},"PeriodicalIF":0.0000,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Fully active frequency compensation analysis on multi-stages CMOS amplifier\",\"authors\":\"Ilghar Rezaei ,&nbsp;Amir Ali Mohammad Khani ,&nbsp;Morteza Dadgar ,&nbsp;Mahdis Attar\",\"doi\":\"10.1016/j.memori.2023.100068\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>An enhanced three-stage CMOS transconductance amplifier attached to a novel frequency compensation network is proposed. Two differential stages are attached with Miller capacitors and the Miller effect is boosted accordingly. In this way, four negative loops intensify the Miller effect virtually. The structure is designed at the transistor level using 0.18 <span><math><mi>μ</mi></math></span>m CMOS library and the SPICE simulator while a symbolical transfer function is extracted and analyzed to obtain circuit dynamics. Leveraging both concept and method, the proposed amplifier shows unconditional stability with acceptable accuracy regarding the symbolic description and simulation results. Ample sensitivity analysis is also provided to show the reliability of the amplifier. By simulation responses, the presented circuit expresses competitive merits against previous works. Simulation results show 120 dB as DC gain, 18 MHz as, GBW, and 54º as phase margin while the simulated amplifier consumes only <span><math><mrow><mn>345</mn><mspace></mspace><mi>μ</mi><mi>W</mi></mrow></math></span>.</p></div>\",\"PeriodicalId\":100915,\"journal\":{\"name\":\"Memories - Materials, Devices, Circuits and Systems\",\"volume\":\"5 \",\"pages\":\"Article 100068\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Memories - Materials, Devices, Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S2773064623000452\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Memories - Materials, Devices, Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2773064623000452","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

提出了一种附加在新型频率补偿网络上的增强型三级CMOS跨导放大器。两个差分级连接有米勒电容器,米勒效应相应地增强。通过这种方式,四个负循环实际上强化了米勒效应。使用0.18μm CMOS库和SPICE模拟器在晶体管级设计了该结构,同时提取并分析了符号传递函数以获得电路动力学。利用概念和方法,所提出的放大器在符号描述和模拟结果方面表现出无条件的稳定性和可接受的准确性。还提供了放大灵敏度分析,以显示放大器的可靠性。通过仿真响应,所提出的电路表达了与先前工作相比的竞争优势。仿真结果表明,当模拟放大器仅消耗345μW时,DC增益为120dB,GBW为18MHz,相位裕度为54º。
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Fully active frequency compensation analysis on multi-stages CMOS amplifier

An enhanced three-stage CMOS transconductance amplifier attached to a novel frequency compensation network is proposed. Two differential stages are attached with Miller capacitors and the Miller effect is boosted accordingly. In this way, four negative loops intensify the Miller effect virtually. The structure is designed at the transistor level using 0.18 μm CMOS library and the SPICE simulator while a symbolical transfer function is extracted and analyzed to obtain circuit dynamics. Leveraging both concept and method, the proposed amplifier shows unconditional stability with acceptable accuracy regarding the symbolic description and simulation results. Ample sensitivity analysis is also provided to show the reliability of the amplifier. By simulation responses, the presented circuit expresses competitive merits against previous works. Simulation results show 120 dB as DC gain, 18 MHz as, GBW, and 54º as phase margin while the simulated amplifier consumes only 345μW.

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