Ring-VCO-based phase-locked loops for clock generation – design considerations and state-of-the-art

This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different applications. Particularly, the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power, jitter and area. An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analytically and benchmarked with respect to their figure-of-merit (FoM). The paper also summarizes the key concerns on the selection of different circuit techniques to optimize the clock performance under different scenarios.