Chip最新文献

Leveraging the low linear and nonlinear absorption loss of silicon at mid-infrared (mid-IR) wavelengths, silicon photonic integrated circuits (PICs) have attracted significant attention for mid-IR applications including optical sensing, spectroscopy, and nonlinear optics. However, mid-IR silicon PICs typically show moderate performance compared to state-of-the-art silicon photonic devices operating in the telecommunication band. Here, we proposed and demonstrated suspended nanomembrane silicon (SNS) PICs with light-guiding within deep-subwavelength waveguide thickness for operation in the short-wavelength mid-IR region. We demonstrated key building components, namely, grating couplers, waveguide arrays, micro-resonators, etc., which exhibit excellent performances in bandwidths, back reflections, quality factors, and fabrication tolerance. Moreover, the results show that the proposed SNS PICs have high compatibility with the multi-project wafer foundry services. Our study provides an unprecedented platform for mid-IR integrated photonics and applications.

In this study, a gallium nitride (GaN) substrate and its 15 μm epitaxial layer were entirely grown by adopting the hydride vapor phase epitaxy (HVPE) technique. To enhance the breakdown voltage (V_BR) of vertical GaN-on-GaN Schottky barrier diodes (SBDs), a dual ion coimplantation of carbon and helium was employed to create the edge termination. The resulting devices exhibited a low turn-on voltage of 0.55 V, a high I_on/I_off ratio of approximately 10⁹, and a low specific on-resistance of 1.93 mΩ cm². When the ion implantation edge was terminated, the maximum V_BR of the devices reached 1575 V, with an average improvement of 126%. These devices demonstrated a high figure of merit (FOM) of 1.28 GW cm^–2 and showed excellent reliability during pulse stress testing.

Reconfigurable field-effect transistors (R-FETs) that can dynamically reconfigure the transistor polarity, from n-type to p-type channel or vice versa, represent a promising new approach to reduce the logic complexity and granularity of programmable electronics. Although R-FETs have been successfully demonstrated upon silicon nanowire (SiNW) channels, a pair of extra program gates is still needed to control the source/drain (S/D) contacts. In this work, we propose a rather simple single gate R-FET structure with an asymmetric S/D electrode contact, where the FET channel polarity can be altered by changing the sign of channel bias V_ds. These R-FETs were fabricated upon an orderly array of planar SiNW channels, grown via in-plane solid-liquid-solid mechanism, and contacted by Ti/Al and Pt/Au at the S/D electrodes, respectively. Remarkably, this channel-bias-controlled R-FET strategy has been successfully testified and implemented upon both p-type-doped (with indium dopants) or n-type-doped (phosphorus) SiNW channels, whereas the R-FET prototypes demonstrate an impressive high I_on/off ratio of > 10⁶ and a steep subthreshold swing of 79 mV/dec. These results indicate a rather simple, compact and generic enough R-FET strategy for the construction of a new generation of SiNW-based programmable and low-power electronics.

The commercially available 4000-Watt continuous-wave (CW) Erbium-doped-fiber laser, emitting at the 1567-nm wavelength where the atmosphere has high transmission, provides an opportunity for harvesting electric power at remote “off the grid” locations using a multi-module photovoltaic (PV) “receiver” panel. This paper proposes a 32-element monocrystalline thick-layer Germanium PV panel for efficient harvesting of a collimated 1.13-m-diam beam. The 0.78-m² PV panel is constructed from commercial Ge wafers. For incident CW laser-beam power in the 4000 to 10,000 W range, our thermal, electrical, and infrared simulations predict 660 to 1510 Watts of electrical output at the panel temperatures of 350 to 423 K.

With the development of 5G technology and increasing chip integration, traditional active cooling methods struggle to meet the growing thermal demands of chips. Thermoelectric coolers (TECs) have garnered great attention due to their rapid response, significant cooling differentials, strong compatibility, high stability and controllable device dimensions. In this review, starting from the fundamental principles of thermoelectric cooling and device design, high-performance thermoelectric cooling materials are summarized, and the progress of advanced on-chip TECs is comprehensively reviewed. Finally, the paper outlines the challenges and opportunities in TEC design, performance and applications, laying great emphasis on the critical role of thermoelectric cooling in addressing the evolving thermal management requirements in the era of emerging chip technologies.